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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq 

update ls1028aqds networking protocol, config in ls1021atwr, env in ls1012a
Add seli3 board support, booke watchdog, update eTSEC support in ppc-qemu
Add DM_SERIAL and lpuart in sl28, add DM_ETH support for some of powerpc platforms

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Tom Rini 2021-04-15 13:11:19 -04:00
parent b86772eda6 20830d0c01
commit 45b3cf88da
103 changed files with 2769 additions and 203 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/Kconfig
View File

@ -162,6 +162,8 @@ config SANDBOX
imply CMD_CLONE
imply SILENT_CONSOLE
imply BOOTARGS_SUBST
imply PHY_FIXED
imply DM_DSA
config SH
bool "SuperH architecture"

39
arch/arm/Kconfig
View File

@ -1463,6 +1463,24 @@ config TARGET_LS1021ATWR
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
config TARGET_PG_WCOM_SELI8
bool "Support Hitachi-Powergrids SELI8 service unit card"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select VENDOR_KM
imply SCSI
help
Support for Hitachi-Powergrids SELI8 service unit card.
SELI8 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A
@ -1587,6 +1605,26 @@ config TARGET_SL28
select ARMV8_MULTIENTRY
select SUPPORT_SPL
select BINMAN
select DM
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_SPI_FLASH
select DM_ETH
select DM_MDIO
select DM_PCI
select DM_RNG
select DM_RTC
select DM_SCSI
select DM_SERIAL
select DM_SPI
select DM_USB
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SPL_DM_I2C if SPL
select SPL_DM_MMC if SPL
select SPL_DM_SERIAL if SPL
help
Support for Kontron SMARC-sAL28 board.
@ -1972,6 +2010,7 @@ source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "board/keymile/Kconfig"
source "arch/arm/Kconfig.debug"

11
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -6,7 +6,9 @@
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <env.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
@ -67,10 +69,19 @@ void spl_board_init(void)
void board_init_f(ulong dummy)
{
int ret;
icache_enable();
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
if (IS_ENABLED(CONFIG_DEBUG_UART))
debug_uart_init();
board_early_init_f();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
timer_init();
#ifdef CONFIG_ARCH_LS2080A
env_init();

2
arch/arm/dts/Makefile
View File

@ -398,6 +398,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \
fsl-ls2080a-rdb.dtb \

12
arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
View File

@ -133,6 +133,14 @@
};
};
#ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE
/ {
chosen {
stdout-path = "serial2:115200n8";
};
};
#endif
#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31
&binman {
fit {
@ -250,6 +258,10 @@
u-boot,dm-pre-reloc;
};
&lpuart1 {
u-boot,dm-pre-reloc;
};
&serial0 {
u-boot,dm-pre-reloc;
};

20
arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
* port 0 USXGMII.
*/
&slot1 {
#include "fsl-sch-30842.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

19
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-30842 cards with AQR112 PHY.
*/
&slot1 {
#include "fsl-sch-30842.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

49
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi Normal file
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@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30841 card with AQR412 10G quad PHY.
*
* Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
* Bottom port is port 0.
* Note that this is only usable for:
* - QDS boards WITHOUT lane B rework,
* - AQR412 card WITHOUT lane A -> lane C rework
*
* The following DTS assumes DIP SW5[1-3] = 000b.
*/
&slot1 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

26
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot1 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

19
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};

63
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi Normal file
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@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
* LS1028A QDS boards with lane B rework require two cards for the 4 switch
* ports, QDS boards without the lane B rework only require one card.
*
* Switch ports are routed as follows:
* Port 0 goes to 1st port of VSC8234 quad card in slot 1,
* Port 1:
* - if the QDS has had lane B rework, it is 1st port in slot 2,
* - otherwise it is 2nd port in slot 1.
* Port 2:
* - if DIP SW5[1] = 0 it is 3rd port in slot 1,
* - otherwise it is 1st port in slot 3.
* Port 3:
* - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
* - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
* - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
*
* The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
* SCH-24801 cards are required in slots 1 and 2.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&slot2 {
#include "fsl-sch-24801.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

48
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
*
*/
/*
* This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
*
* Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
* Top port is port 0.
*
* The following DTS assumes DIP SW5[1-3] = 000b.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

48
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
* is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
*
* We're including the normal .dsti file, not the reworked card .dtsi
* intentionally. We are using multiplexing of the 4 interfaces on a single
* lane and the rework doesn't actually disable any port. The rework is in fact
* needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
* card.
*/
&slot2 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};

42
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
* This is only available on LS1028A QDS boards with lane B rework.
*/
&slot2 {
#include "fsl-sch-28021.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};

20
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot2 {
#include "fsl-sch-30842.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};

20
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot3 {
#include "fsl-sch-30842.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};

3
arch/arm/dts/fsl-ls1028a-qds.dtsi
View File

@ -258,3 +258,6 @@
&mdio0 {
status = "okay";
};
#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"

28
arch/arm/dts/fsl-sch-24801.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-24801 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
* It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
* PHY addresses are 0x1c - 0x1f.
* On the card the first port is the top port (farthest from PEX connector).
*/
phy@1c {
reg = <0x1c>;
};
phy@1d {
reg = <0x1d>;
};
phy@1e {
reg = <0x1e>;
};
phy@1f {
reg = <0x1f>;
};

29
arch/arm/dts/fsl-sch-28021.dtsi Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-28021 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
* It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
* single QSGMII lane.
* PHY addresses are 0x08 - 0x0b.
* On the card the first port is the top port (farthest from PEX connector).
*/
phy@08 {
reg = <0x08>;
};
phy@09 {
reg = <0x09>;
};
phy@0a {
reg = <0x0a>;
};
phy@0b {
reg = <0x0b>;
};

38
arch/arm/dts/fsl-sch-30841.dtsi Normal file
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@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-30841 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/
phy@00 {
reg = <0x00>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};
phy@01 {
reg = <0x01>;
mdi-reversal = <1>;
smb-addr = <0x26>;
};
phy@02 {
reg = <0x02>;
mdi-reversal = <1>;
smb-addr = <0x27>;
};
phy@03 {
reg = <0x03>;
mdi-reversal = <1>;
smb-addr = <0x28>;
};

18
arch/arm/dts/fsl-sch-30842.dtsi Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-30842 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
* SGMII-2500, USXGMII, XFI.
* PHY address is 0x02.
*/
phy@02 {
reg = <0x02>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};

111
arch/arm/dts/ls1021a-pg-wcom-seli8.dts Normal file
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@ -0,0 +1,111 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
model = "Hitachi-Powergrids SELI8 Service Unit for XMC and FOX";
chosen {
stdout-path = &uart0;
};
};
&enet0 {
status = "okay";
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet1 {
status = "okay";
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
status = "okay";
};
&i2c0 {
status = "okay";
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
ranges = <0x0 0x0 0x60000000 0x04000000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "rcw";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "qe";
reg = <0x20000 0x20000>;
};
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
};
partition@60000 {
label = "env";
reg = <0x60000 0x20000>;
};
partition@100000 {
label = "u-boot";
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
};
};
};
&mdio0 {
debug_phy: ethernet-phy@11 {
reg = <0x11>;
};
tbi0: tbi-phy@0xb {
reg = <0xb>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@0xd {
reg = <0xd>;
device_type = "tbi-phy";
};
};
&uart0 {
status = "okay";
};

2
arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
View File

@ -30,7 +30,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy14>;
};
mdio@f1000 {
mdio@5f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
View File

@ -30,7 +30,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy15>;
};
mdio@f3000 {
mdio@5f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy8>;
};
mdio@e1000 {
mdio@5e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy9>;
};
mdio@e3000 {
mdio@5e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy10>;
};
mdio@e5000 {
mdio@5e5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy11>;
};
mdio@e7000 {
mdio@5e7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy12>;
};
mdio@e9000 {
mdio@5e9000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

2
arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
View File

@ -29,7 +29,7 @@ fman@500000 {
pcsphy-handle = <&pcsphy13>;
};
mdio@eb000 {
mdio@5eb000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

4
arch/powerpc/dts/qoriq-fman3-1.dtsi
View File

@ -61,14 +61,14 @@ fman1: fman@500000 {
reg = <0x87000 0x1000>;
};
mdio1: mdio@fc000 {
mdio1: mdio@5fc000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfc000 0x1000>;
};
mdio@fd000 {
mdio@5fd000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

55
arch/powerpc/dts/t1042d4rdb.dts
View File

@ -3,7 +3,7 @@
* T1042D4RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2021 NXP
*/
/include/ "t104x.dtsi"
@ -20,6 +20,57 @@
};
};
&soc {
fman0: fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
mdio0: mdio@fc000 {
phy_sgmii_0: ethernet-phy@2 {
reg = <0x02>;
};
phy_sgmii_1: ethernet-phy@3 {
reg = <0x03>;
};
phy_sgmii_2: ethernet-phy@1 {
reg = <0x01>;
};
phy_rgmii_0: ethernet-phy@4 {
reg = <0x04>;
};
phy_rgmii_1: ethernet-phy@5 {
reg = <0x05>;
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
@ -30,3 +81,5 @@
spi-max-frequency = <10000000>; /* input clock */
};
};
/include/ "t1042si-post.dtsi"

46
arch/powerpc/dts/t1042si-post.dtsi Normal file
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* T1042 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
* Copyright 2021 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
/include/ "qoriq-fman3-0-1g-1.dtsi"
/include/ "qoriq-fman3-0-1g-2.dtsi"
/include/ "qoriq-fman3-0-1g-3.dtsi"
/include/ "qoriq-fman3-0-1g-4.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
mdio@fc000 {
interrupts = <100 1 0 0>;
};
mdio@fd000 {
status = "disabled";
};
};
};

69
arch/powerpc/dts/t2080rdb.dts
View File

@ -3,7 +3,7 @@
* T2080RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2021 NXP
*/
/include/ "t2080.dtsi"
@ -20,6 +20,71 @@
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
@ -38,3 +103,5 @@
reg = <0x68>;
};
};
/include/ "t2080si-post.dtsi"

51
arch/powerpc/dts/t2080si-post.dtsi Normal file
View File

@ -0,0 +1,51 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* T2080 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2021 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi"
/include/ "qoriq-fman3-0-1g-2.dtsi"
/include/ "qoriq-fman3-0-1g-3.dtsi"
/include/ "qoriq-fman3-0-10g-0.dtsi"
/include/ "qoriq-fman3-0-10g-1.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet6: ethernet@f0000 {
};
enet7: ethernet@f2000 {
};
mdio@fc000 {
interrupts = <100 1 0 0>;
};
mdio@fd000 {
interrupts = <101 1 0 0>;
};
};
};

142
arch/powerpc/dts/t4240rdb.dts
View File

@ -3,7 +3,7 @@
* T4240RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2021 NXP
*/
/include/ "t4240.dtsi"
@ -20,6 +20,144 @@
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy21>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy22>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy23>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy24>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy41>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy42>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy43>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy44>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy4>;
phy-connection-type = "xgmii";
};
mdio@5fc000 {
sgmiiphy21: ethernet-phy@0 {
reg = <0x0>;
};
sgmiiphy22: ethernet-phy@1 {
reg = <0x1>;
};
sgmiiphy23: ethernet-phy@2 {
reg = <0x2>;
};
sgmiiphy24: ethernet-phy@3 {
reg = <0x3>;
};
sgmiiphy41: ethernet-phy@4 {
reg = <0x4>;
};
sgmiiphy42: ethernet-phy@5 {
reg = <0x5>;
};
sgmiiphy43: ethernet-phy@6 {
reg = <0x6>;
};
sgmiiphy44: ethernet-phy@7 {
reg = <0x7>;
};
};
mdio@5fd000 {
xfiphy1: ethernet-phy@10 {
compatible = "ethernet-phy-id13e5.1002";
reg = <0x10>;
};
xfiphy2: ethernet-phy@11 {
compatible = "ethernet-phy-id13e5.1002";
reg = <0x11>;
};
xfiphy3: ethernet-phy@13 {
compatible = "ethernet-phy-id13e5.1002";
reg = <0x13>;
};
xfiphy4: ethernet-phy@12 {
compatible = "ethernet-phy-id13e5.1002";
reg = <0x12>;
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
@ -30,3 +168,5 @@
spi-max-frequency = <10000000>; /* input clock */
};
};
/include/ "t4240si-post.dtsi"

101
arch/powerpc/dts/t4240si-post.dtsi Normal file
View File

@ -0,0 +1,101 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* T4240 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2021 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
/include/ "qoriq-fman3-0-1g-1.dtsi"
/include/ "qoriq-fman3-0-1g-2.dtsi"
/include/ "qoriq-fman3-0-1g-3.dtsi"
/include/ "qoriq-fman3-0-1g-4.dtsi"
/include/ "qoriq-fman3-0-1g-5.dtsi"
/include/ "qoriq-fman3-0-10g-0.dtsi"
/include/ "qoriq-fman3-0-10g-1.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@ea000 {
};
enet6: ethernet@f0000 {
};
enet7: ethernet@f2000 {
};
mdio@fc000 {
status = "disabled";
};
mdio@fd000 {
status = "disabled";
};
};
/include/ "qoriq-fman3-1.dtsi"
/include/ "qoriq-fman3-1-1g-0.dtsi"
/include/ "qoriq-fman3-1-1g-1.dtsi"
/include/ "qoriq-fman3-1-1g-2.dtsi"
/include/ "qoriq-fman3-1-1g-3.dtsi"
/include/ "qoriq-fman3-1-1g-4.dtsi"
/include/ "qoriq-fman3-1-1g-5.dtsi"
/include/ "qoriq-fman3-1-10g-0.dtsi"
/include/ "qoriq-fman3-1-10g-1.dtsi"
fman@500000 {
enet8: ethernet@e0000 {
};
enet9: ethernet@e2000 {
};
enet10: ethernet@e4000 {
};
enet11: ethernet@e6000 {
};
enet12: ethernet@e8000 {
};
enet13: ethernet@ea000 {
};
enet14: ethernet@f0000 {
};
enet15: ethernet@f2000 {
};
mdio@5fc000 {
interrupts = <100 1 0 0>;
};
mdio@5fd000 {
interrupts = <101 1 0 0>;
};
};
};

44
arch/sandbox/dts/test.dts
View File

@ -15,7 +15,9 @@
aliases {
console = &uart0;
eth0 = "/eth@10002000";
eth2 = &swp_0;
eth3 = &eth_3;
eth4 = &dsa_eth0;
eth5 = &eth_5;
gpio1 = &gpio_a;
gpio2 = &gpio_b;
@ -478,6 +480,48 @@
fake-host-hwaddr = [00 00 66 44 22 22];
};
dsa_eth0: dsa-test-eth {
compatible = "sandbox,eth";
reg = <0x10006000 0x1000>;
fake-host-hwaddr = [00 00 66 44 22 66];
};
dsa-test {
compatible = "sandbox,dsa";
ports {
#address-cells = <1>;
#size-cells = <0>;
swp_0: port@0 {
reg = <0>;
label = "lan0";
phy-mode = "rgmii-rxid";
fixed-link {
speed = <100>;
full-duplex;
};
};
swp_1: port@1 {
reg = <1>;
label = "lan1";
phy-mode = "rgmii-txid";
fixed-link = <0 1 100 0 0>;
};
port@2 {
reg = <2>;
ethernet = <&dsa_eth0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
firmware {
sandbox_firmware: sandbox-firmware {
compatible = "sandbox,firmware";

6
board/emulation/qemu-ppce500/Kconfig
View File

@ -9,4 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "qemu-ppce500"
config PLATFORM_BUS_MAP_ADDR
hex
default 0xf0000000
help
The QEMU platform bus base mapped address in the virtual memory space.
endif

29
board/emulation/qemu-ppce500/qemu-ppce500.c
View File

@ -14,6 +14,8 @@
#include <net.h>
#include <pci.h>
#include <time.h>
#include <dm/simple_bus.h>
#include <dm/uclass-internal.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
@ -109,6 +111,17 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
return 0;
}
static void platform_bus_map_region(ulong map_addr, phys_addr_t paddr,
phys_size_t size)
{
/* Align map_addr */
map_addr += size - 1;
map_addr &= ~(size - 1);
/* Map virtual memory for range */
assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
}
int misc_init_r(void)
{
struct udevice *dev;
@ -148,6 +161,22 @@ int misc_init_r(void)
*/
disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
/*
* Detect the presence of the platform bus node, and
* create a virtual memory mapping for it.
*/
for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev);
dev;
ret = uclass_find_next_device(&dev)) {
if (device_is_compatible(dev, "qemu,platform")) {
struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
platform_bus_map_region(CONFIG_PLATFORM_BUS_MAP_ADDR,
plat->target, plat->size);
break;
}
}
return 0;
}

8
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define VERSION_MASK 0x00FF
#define BANK_MASK 0x0001
#define CONFIG_RESET 0x1
#define CFG_RESET 0x1
#define INIT_RESET 0x1
#define CPLD_SET_MUX_SERDES 0x20
@ -283,7 +283,7 @@ static void convert_serdes_mux(int type, int need_reset)
if (need_reset == 1) {
printf("Reset board to enable configuration\n");
cpld_data->system_rst = CONFIG_RESET;
cpld_data->system_rst = CFG_RESET;
}
}
@ -612,7 +612,7 @@ static void convert_flash_bank(char bank)
cpld_data->vbank = bank;
printf("Reset board to enable configuration.\n");
cpld_data->system_rst = CONFIG_RESET;
cpld_data->system_rst = CFG_RESET;
}
static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
@ -644,7 +644,7 @@ static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc > 2)
return CMD_RET_USAGE;
if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
cpld_data->system_rst = CONFIG_RESET;
cpld_data->system_rst = CFG_RESET;
else if (strcmp(argv[1], "init") == 0)
cpld_data->global_rst = INIT_RESET;
else

35
board/freescale/t208xrdb/eth_t208xrdb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
@ -104,6 +105,40 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
* "fsl,dpa-ethernet" nodes that reference them.
*/
void fdt_fixup_board_fman_ethernet(void *fdt)
{
int mac_off, eth_off, i;
char mac_path[2][42] = {
"/soc@ffe000000/fman@400000/ethernet@e8000",
"/soc@ffe000000/fman@400000/ethernet@ea000",
};
u32 eth_ph;
for (i = 0; i < 2; i++) {
/* Disable the MAC node */
mac_off = fdt_path_offset(fdt, mac_path[i]);
if (mac_off < 0)
continue;
fdt_status_disabled(fdt, mac_off);
/* Disable the fsl,dpa-ethernet node that points to the MAC.
* The fsl,fman-mac property refers to the MAC's phandle.
*/
eth_ph = fdt_get_phandle(fdt, mac_off);
if (eth_ph <= 0)
continue;
eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac",
&eth_ph,
sizeof(eth_ph));
if (eth_off >= 0)
fdt_status_disabled(fdt, eth_off);
}
}
void fdt_fixup_board_enet(void *fdt)
{
return;

3
board/freescale/t208xrdb/t208xrdb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2013 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -137,6 +138,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#else
fdt_fixup_board_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t208xrdb/t208xrdb.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#ifndef __CORENET_DS_H__
@ -8,5 +9,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
#endif

23
board/keymile/Kconfig
View File

@ -20,8 +20,8 @@ config KM_PNVRAM
config KM_PHRAM
hex "Physical RAM"
default 0x17F000 if ARM
default 0x100000 if PPC
default 0x17F000 if ARM && !ARCH_LS1021A
default 0x100000 if PPC || ARCH_LS1021A
depends on !ARCH_SOCFPGA
help
Start address of the physical RAM, which is the mounted /var folder.
@ -30,13 +30,14 @@ config KM_RESERVED_PRAM
hex "Reserved RAM"
default 0x801000 if ARCH_KIRKWOOD
default 0x0 if MPC83xx
default 0x1000 if MPC85xx
default 0x1000 if MPC85xx || ARCH_LS1021A
depends on !ARCH_SOCFPGA
help
Reserved physical RAM area at the end of memory for special purposes.
config KM_CRAMFS_ADDR
hex "CRAMFS Address"
default 0x83000000 if ARCH_LS1021A
default 0x3000000
depends on !ARCH_SOCFPGA
help
@ -44,16 +45,25 @@ config KM_CRAMFS_ADDR
config KM_KERNEL_ADDR
hex "Kernel Load Address"
default 0x82000000 if ARCH_LS1021A
default 0x2000000
help
Address where to load Linux kernel in RAM.
config KM_FDT_ADDR
hex "FDT Load Address"
default 0x82FC0000 if ARCH_LS1021A
default 0x2FC0000
help
Address where to load flattened device tree in RAM.
config SYS_PAX_BASE
hex "PAX IFC Base Address"
default 0x78000000
depends on ARCH_LS1021A
help
IFC Base Address for PAXx FPGA.
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"
@ -69,9 +79,9 @@ config KM_DEF_NETDEV
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
default y if ARCH_KIRKWOOD || MPC83xx
default n if MPC85xx || ARCH_SOCFPGA
default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A
help
Use the Ethernet initialization implemented in common code, which
Use the Ethernet initialization implemented in common code that
detects if a Piggy board is present.
config PIGGY_MAC_ADDRESS_OFFSET
@ -90,7 +100,7 @@ config KM_MVEXTSW_ADDR
config KM_IVM_BUS
int "IVM I2C Bus"
default 0 if ARCH_SOCFPGA
default 1 if ARCH_KIRKWOOD || MPC85xx
default 1 if ARCH_KIRKWOOD || MPC85xx || ARCH_LS1021A
default 2 if MPC83xx
help
Identifier number of I2C bus, where the inventory EEPROM is connected to.
@ -117,6 +127,7 @@ source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/keymile/pg-wcom-ls102xa/Kconfig"
endmenu

19
board/keymile/common/ivm.c
View File

@ -306,11 +306,7 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
return 0;
page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2];
if (!IS_ENABLED(CONFIG_KMTEGR1)) {
/* if an offset is defined, add it */
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"ethaddr", (char *)valbuf);
} else {
if (IS_ENABLED(CONFIG_KMTEGR1)) {
/* KMTEGR1 has a special setup. eth0 has no connection to the
* outside and gets an locally administred MAC address, eth1 is
* the debug interface and gets the official MAC address from
@ -320,6 +316,19 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
env_set((char *)"ethaddr", (char *)valbuf);
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
} else if (IS_ENABLED(CONFIG_ARCH_LS1021A)) {
/* LS102xA has 1xRGMII for debug connection and
* 2xSGMII for back-plane mgmt connection
*/
process_mac(valbuf, page2, 1, true);
env_set((char *)"ethaddr", (char *)valbuf);
process_mac(valbuf, page2, 2, true);
env_set((char *)"eth1addr", (char *)valbuf);
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth2addr", (char *)valbuf);
} else {
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"ethaddr", (char *)valbuf);
}
if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
/* 3rd ethernet interface */

19
board/keymile/pg-wcom-ls102xa/Kconfig Normal file
View File

@ -0,0 +1,19 @@
if TARGET_PG_WCOM_SELI8
config SYS_BOARD
default "pg-wcom-ls102xa"
config SYS_VENDOR
default "keymile"
config SYS_SOC
default "ls102xa"
config SYS_CONFIG_NAME
default "pg-wcom-seli8"
config BOARD_SPECIFIC_OPTIONS
def_bool y
imply FS_CRAMFS
endif

10
board/keymile/pg-wcom-ls102xa/MAINTAINERS Normal file
View File

@ -0,0 +1,10 @@
Hitachi Power Grids LS102XA BOARD
M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
M: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
M: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com>
S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
F: include/configs/pg-wcom-seli8.h
F: configs/pg_wcom_seli8_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts

11
board/keymile/pg-wcom-ls102xa/Makefile Normal file
View File

@ -0,0 +1,11 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2021 Hitachi Power Grids. All rights reserved.
#
obj-y += pg-wcom-ls102xa.o ddr.o
obj-y += ../common/common.o ../common/ivm.o ../common/qrio.o
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o
obj-$(CONFIG_LS102XA_STREAM_ID) += ../../freescale/common/ls102xa_stream_id.o
obj-$(CONFIG_ID_EEPROM) += ../../freescale/common/sys_eeprom.o

91
board/keymile/pg-wcom-ls102xa/ddr.c Normal file
View File

@ -0,0 +1,91 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <asm/arch/ls102xa_soc.h>
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
// 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock)
popts->clk_adjust = 0x4;
popts->write_data_delay = 0x4;
// wr leveling start value for lane 0
popts->wrlvl_start = 0x5;
// wr leveling start values for lanes 1-3 (lane 4 not there)
popts->wrlvl_ctl_2 = 0x05050500;
// 32-bit DRAM, no need to set start values for lanes we do not have (5-8)
popts->wrlvl_ctl_3 = 0x0;
popts->cpo_override = 0x1f;
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
popts->otf_burst_chop_en = 0;
popts->burst_length = DDR_BL8;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
popts->cswl_override = DDR_CSWL_CS0;
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x58;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
int fsl_initdram(void)
{
phys_size_t dram_size;
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
erratum_a008850_post();
gd->ram_size = dram_size;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}

160
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c Normal file
View File

@ -0,0 +1,160 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_immap.h>
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <fsl_ddr.h>
#include <spl.h>
#include <fdt_support.h>
#include <fsl_qe.h>
#include <fsl_validate.h>
#include "../common/common.h"
#include "../common/qrio.h"
DECLARE_GLOBAL_DATA_PTR;
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
{
show_qrio();
return 0;
}
int dram_init(void)
{
return fsl_initdram();
}
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */
setbits_be32(&gur->ddrclkdr, 2);
/* IFC Global Configuration */
setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
IFC_CCR_INV_CLK_EN);
/* clear BD & FR bits for BE BD's and frame data */
clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
init_early_memctl_regs();
/* QRIO Configuration */
qrio_uprstreq(UPREQ_CORE_RST);
if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
}
i2c_deblock_gpio_cfg();
arch_soc_init();
return 0;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
erratum_a010315();
fsl_serdes_init();
ls102xa_smmu_stream_id_init();
u_qe_init();
return 0;
}
int board_late_init(void)
{
return 0;
}
int misc_init_r(void)
{
if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
if (IS_ENABLED(CONFIG_PCI))
ft_pci_setup(blob, bd);
return 0;
}
u8 flash_read8(void *addr)
{
return __raw_readb(addr + 1);
}
void flash_write16(u16 val, void *addr)
{
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
__raw_writew(shftval, addr);
}
u16 flash_read16(void *addr)
{
u16 val = __raw_readw(addr);
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
int hush_init_var(void)
{
ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
int last_stage_init(void)
{
set_km_env();
return 0;
}

10
board/kontron/sl28/Kconfig
View File

@ -48,4 +48,14 @@ config SL28_BL32_ENTRY_ADDR
endif
config SL28_ENABLE_SER0_CONSOLE
bool "Enable console output on SER0"
select DM_SERIAL
select SPL_DM_SERIAL
select FSL_LPUART
help
By default the console output of this board is on the second serial
line (SER1). Sometimes it is desirable to enable output on the first
serial line (SER0). For example, if you have a carrier which only
supports the first serial port.
endif

2
board/kontron/sl28/Makefile
View File

@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD
obj-y += sl28.o cmds.o
endif
obj-y += ddr.o
obj-y += common.o ddr.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o

11
board/kontron/sl28/common.c Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
u32 get_lpuart_clk(void)
{
return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
}

3
configs/T1042D4RDB_NAND_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -66,6 +67,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -63,6 +64,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

8
configs/T1042D4RDB_SECURE_BOOT_defconfig
View File

@ -2,8 +2,10 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -17,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -29,6 +32,7 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
@ -45,8 +49,9 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
@ -60,4 +65,3 @@ CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

3
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -65,6 +66,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/T1042D4RDB_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -51,6 +52,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/T2080RDB_NAND_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -70,6 +71,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T2080RDB_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -67,6 +68,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T2080RDB_SPIFLASH_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -69,6 +70,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T2080RDB_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -54,6 +55,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T4240RDB_SDCARD_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -59,6 +60,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/T4240RDB_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -47,6 +48,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

17
configs/kontron_sl28_defconfig
View File

@ -8,8 +8,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x3e0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x18010000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_SPL_SERIAL_SUPPORT=y
@ -35,7 +33,6 @@ CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@ -58,52 +55,38 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_NXP_FSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y

70
configs/pg_wcom_seli8_defconfig Normal file
View File

@ -0,0 +1,70 @@
CONFIG_ARM=y
CONFIG_TARGET_PG_WCOM_SELI8=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_FSL_DDR3=y
# CONFIG_MMC is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y

5
configs/qemu-ppce500_defconfig
View File

@ -27,15 +27,20 @@ CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
CONFIG_BLK=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
# CONFIG_MMC is not set
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
CONFIG_PCI_MPC85XX=y
CONFIG_DM_RTC=y

5
doc/board/emulation/qemu-ppce500.rst
View File

@ -70,6 +70,11 @@ interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by::
$ qemu-system-ppc -nographic -machine ppce500 -bios u-boot \
-nic tap,ifname=tap0,script=no,downscript=no,model=e1000
The QEMU ppce500 machine can also dynamically instantiate an eTSEC device if
"-device eTSEC" is given to QEMU::
-netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0
VirtIO BLK driver is also enabled to support booting from a disk image where
a kernel image is stored. Append the following to QEMU::

46
doc/device-tree-bindings/net/fixed-link.txt
View File

@ -5,21 +5,37 @@ Some Ethernet MACs have a "fixed link", and are not connected to a
normal MDIO-managed PHY device. For those situations, a Device Tree
binding allows to describe a "fixed link".
Such a fixed link situation is described by creating a 'fixed-link'
sub-node of the Ethernet MAC device node, with the following
properties:
Note there are two ways to describe a fixed PHY attached to an
Ethernet device:
* 'speed' (integer, mandatory), to indicate the link speed. Accepted
values are 10, 100 and 1000
* 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed.
* 'pause' (boolean, optional), to indicate that pause should be
enabled.
* 'asym-pause' (boolean, optional), to indicate that asym_pause should
be enabled.
- The new DT binding, where 'fixed-link' is a sub-node of the Ethernet
MAC device node, with the following properties:
* 'speed' (integer, mandatory), to indicate the link speed. Accepted
values are 10, 100 and 1000
* 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed.
* 'pause' (boolean, optional), to indicate that pause should be
enabled.
* 'asym-pause' (boolean, optional), to indicate that asym_pause should
be enabled.
- The old DT binding, where 'fixed-link' is a property with 5 cells
encoding various information about the fixed PHY, in the form of
<phy_id, full-duplex, speed, pause, asym-pause>.
* 'phy_id', emulated PHY ID, choose any but unique to the all specified
fixed-links. Note U-Boot deliberately ignores the 'phy_id' and
unconditionally uses PHY_FIXED_ID.
* 'full-duplex', 0 for half duplex or 1 for full duplex
* 'speed', link speed in Mbits/sec, accepts only 10, 100 and 1000
* 'pause', 0 for no pause, 1 for pause
* 'asym-pause', 0 for no asymmetric pause, 1 for asymmetric pause
Examples:
The new binding:
ethernet@0 {
...
fixed-link {
@ -28,3 +44,11 @@ ethernet@0 {
};
...
};
The old binding:
ethernet@0 {
...
fixed-link = <0 1 1000 0 0>;
...
};

19
doc/device-tree-bindings/net/fsl-tsec-phy.txt
View File

@ -3,12 +3,17 @@
Properties:
- compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- reg : Offset and length of the register set for the device. If this is
missing, a subnode with a name prefix "queue-group" must be provided to
provide the <reg> property.
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
property is only really needed if the connection is of type "rgmii-id",
"rgmii-rxid" and "rgmii-txid" as all other connection types are detected
by hardware.
- ranges : an <empty> value if subnode "queue-group" is present, specifying
that no address translation is required between them TSEC parent node and
the child "queue-group" node.
Example:
ethernet@24000 {
@ -18,6 +23,18 @@ Example:
phy-connection-type = "sgmii";
};
An alternate description with "queue-group" subnode example:
ethernet@24000 {
compatible = "fsl,etsec2";
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
ranges;
queue-group {
reg = <0x24000 0x1000>;
};
};
Child nodes of the TSEC controller are typically the individual PHY devices
connected via the MDIO bus (sometimes the MDIO bus controller is separate).

14
drivers/core/Kconfig
View File

@ -235,6 +235,20 @@ config SPL_SIMPLE_BUS
Supports the 'simple-bus' driver, which is used on some systems
in SPL.
config SIMPLE_BUS_CORRECT_RANGE
bool "Decode the 'simple-bus' <range> by honoring the #address-cells and #size-cells"
depends on SIMPLE_BUS
default y if SANDBOX
help
Decoding the 'simple-bus' <range> by honoring the #address-cells
and #size-cells of parent/child bus. If unset, #address-cells of
parent bus is assumed to be 1, #address-cells and #size-cells of
child bus is also assumed to be 1, to save some spaces of using
an advanced API to decode the <range>, which benefits SPL image
builds that have size limits.
If you are unsure about this, Say N here.
config SIMPLE_PM_BUS
bool "Support simple-pm-bus driver"
depends on DM && OF_CONTROL && CLK && POWER_DOMAIN

23
drivers/core/of_extra.c
View File

@ -130,3 +130,26 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type,
return 0;
}
bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node)
{
ofnode node, subnode;
int len;
subnode = ofnode_find_subnode(eth_node, "fixed-link");
if (ofnode_valid(subnode)) {
/* new binding */
node = subnode;
} else if (ofnode_get_property(eth_node, "fixed-link", &len) &&
len == (5 * sizeof(__be32))) {
/* old binding */
node = eth_node;
} else {
return false;
}
if (phy_node)
*phy_node = node;
return true;
}

32
drivers/core/simple-bus.c
View File

@ -4,8 +4,12 @@
*/
#include <common.h>
#include <asm/global_data.h>
#include <dm.h>
#include <dm/simple_bus.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr)
{
@ -22,16 +26,30 @@ static int simple_bus_post_bind(struct udevice *dev)
#if CONFIG_IS_ENABLED(OF_PLATDATA)
return 0;
#else
u32 cell[3];
struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
int ret;
ret = dev_read_u32_array(dev, "ranges", cell, ARRAY_SIZE(cell));
if (!ret) {
struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
if (CONFIG_IS_ENABLED(SIMPLE_BUS_CORRECT_RANGE)) {
uint64_t caddr, paddr, len;
plat->base = cell[0];
plat->target = cell[1];
plat->size = cell[2];
/* only read range index 0 */
ret = fdt_read_range((void *)gd->fdt_blob, dev_of_offset(dev),
0, &caddr, &paddr, &len);
if (!ret) {
plat->base = caddr;
plat->target = paddr;
plat->size = len;
}
} else {
u32 cell[3];
ret = dev_read_u32_array(dev, "ranges", cell,
ARRAY_SIZE(cell));
if (!ret) {
plat->base = cell[0];
plat->target = cell[1];
plat->size = cell[2];
}
}
return dm_scan_fdt_dev(dev);

9
drivers/net/Kconfig
View File

@ -78,6 +78,15 @@ config DM_ETH_PHY
help
Enable driver model for Ethernet Generic PHY .
config DSA_SANDBOX
depends on DM_DSA && SANDBOX
default y
bool "Sandbox: Mocked DSA driver"
help
This driver implements a dummy DSA switch connected to a dummy sandbox
Ethernet device used as DSA master, to test DSA class code, including
exported DSA API and datapath processing of Ethernet traffic.
menuconfig NETDEVICES
bool "Network device support"
depends on NET

1
drivers/net/Makefile
View File

@ -23,6 +23,7 @@ obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o

179
drivers/net/dsa_sandbox.c Normal file
View File

@ -0,0 +1,179 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP Semiconductors
*/
#include <asm/eth.h>
#include <net/dsa.h>
#include <net.h>
#define DSA_SANDBOX_MAGIC 0x00415344
#define DSA_SANDBOX_TAG_LEN sizeof(struct dsa_sandbox_tag)
struct dsa_sandbox_priv {
struct eth_sandbox_priv *master_priv;
int port_en_mask;
};
struct dsa_sandbox_tag {
u32 magic;
u32 port;
};
static bool sb_dsa_port_enabled(struct udevice *dev, int port)
{
struct dsa_sandbox_priv *priv = dev_get_priv(dev);
return priv->port_en_mask & BIT(port);
}
static bool sb_dsa_master_enabled(struct udevice *dev)
{
struct dsa_sandbox_priv *priv = dev_get_priv(dev);
return !priv->master_priv->disabled;
}
static int dsa_sandbox_port_enable(struct udevice *dev, int port,
struct phy_device *phy)
{
struct dsa_sandbox_priv *priv = dev_get_priv(dev);
if (!sb_dsa_master_enabled(dev))
return -EFAULT;
priv->port_en_mask |= BIT(port);
return 0;
}
static void dsa_sandbox_port_disable(struct udevice *dev, int port,
struct phy_device *phy)
{
struct dsa_sandbox_priv *priv = dev_get_priv(dev);
priv->port_en_mask &= ~BIT(port);
}
static int dsa_sandbox_xmit(struct udevice *dev, int port, void *packet,
int length)
{
struct dsa_sandbox_tag *tag = packet;
if (!sb_dsa_master_enabled(dev))
return -EFAULT;
if (!sb_dsa_port_enabled(dev, port))
return -EFAULT;
tag->magic = DSA_SANDBOX_MAGIC;
tag->port = port;
return 0;
}
static int dsa_sandbox_rcv(struct udevice *dev, int *port, void *packet,
int length)
{
struct dsa_sandbox_tag *tag = packet;
if (!sb_dsa_master_enabled(dev))
return -EFAULT;
if (tag->magic != DSA_SANDBOX_MAGIC)
return -EFAULT;
*port = tag->port;
if (!sb_dsa_port_enabled(dev, tag->port))
return -EFAULT;
return 0;
}
static const struct dsa_ops dsa_sandbox_ops = {
.port_enable = dsa_sandbox_port_enable,
.port_disable = dsa_sandbox_port_disable,
.xmit = dsa_sandbox_xmit,
.rcv = dsa_sandbox_rcv,
};
static int sb_dsa_handler(struct udevice *dev, void *packet,
unsigned int len)
{
struct eth_sandbox_priv *master_priv;
struct dsa_sandbox_tag *tag = packet;
struct udevice *dsa_dev;
u32 port_index;
void *rx_buf;
int i;
/* this emulates the switch hw and the network side */
if (tag->magic != DSA_SANDBOX_MAGIC)
return -EFAULT;
port_index = tag->port;
master_priv = dev_get_priv(dev);
dsa_dev = master_priv->priv;
if (!sb_dsa_port_enabled(dsa_dev, port_index))
return -EFAULT;
packet += DSA_SANDBOX_TAG_LEN;
len -= DSA_SANDBOX_TAG_LEN;
if (!sandbox_eth_arp_req_to_reply(dev, packet, len))
goto dsa_tagging;
if (!sandbox_eth_ping_req_to_reply(dev, packet, len))
goto dsa_tagging;
return 0;
dsa_tagging:
master_priv->recv_packets--;
i = master_priv->recv_packets;
rx_buf = master_priv->recv_packet_buffer[i];
len = master_priv->recv_packet_length[i];
memmove(rx_buf + DSA_SANDBOX_TAG_LEN, rx_buf, len);
tag = rx_buf;
tag->magic = DSA_SANDBOX_MAGIC;
tag->port = port_index;
len += DSA_SANDBOX_TAG_LEN;
master_priv->recv_packet_length[i] = len;
master_priv->recv_packets++;
return 0;
}
static int dsa_sandbox_probe(struct udevice *dev)
{
struct dsa_sandbox_priv *priv = dev_get_priv(dev);
struct udevice *master = dsa_get_master(dev);
struct eth_sandbox_priv *master_priv;
if (!master)
return -ENODEV;
dsa_set_tagging(dev, DSA_SANDBOX_TAG_LEN, 0);
master_priv = dev_get_priv(master);
master_priv->priv = dev;
master_priv->tx_handler = sb_dsa_handler;
priv->master_priv = master_priv;
return 0;
}
static const struct udevice_id dsa_sandbox_ids[] = {
{ .compatible = "sandbox,dsa" },
{ }
};
U_BOOT_DRIVER(dsa_sandbox) = {
.name = "dsa_sandbox",
.id = UCLASS_DSA,
.of_match = dsa_sandbox_ids,
.probe = dsa_sandbox_probe,
.ops = &dsa_sandbox_ops,
.priv_auto = sizeof(struct dsa_sandbox_priv),
};

1
drivers/net/phy/Kconfig
View File

@ -292,6 +292,7 @@ config PHY_XILINX
config PHY_XILINX_GMII2RGMII
bool "Xilinx GMII to RGMII Ethernet PHYs support"
depends on DM_ETH
help
This adds support for Xilinx GMII to RGMII IP core. This IP acts
as bridge between MAC connected over GMII and external phy that

54
drivers/net/phy/fixed.c
View File

@ -15,18 +15,42 @@
DECLARE_GLOBAL_DATA_PTR;
int fixedphy_probe(struct phy_device *phydev)
static int fixedphy_probe(struct phy_device *phydev)
{
/* fixed-link phy must not be reset by core phy code */
phydev->flags |= PHY_FLAG_BROKEN_RESET;
return 0;
}
static int fixedphy_config(struct phy_device *phydev)
{
ofnode node = phy_get_ofnode(phydev);
struct fixed_link *priv;
int ofnode = phydev->addr;
bool old_binding = false;
u32 old_val[5];
u32 val;
if (!ofnode_valid(node))
return -EINVAL;
/* check for mandatory properties within fixed-link node */
val = fdt_getprop_u32_default_node(gd->fdt_blob,
ofnode, 0, "speed", 0);
val = ofnode_read_u32_default(node, "speed", 0);
if (!val) {
/* try old binding */
old_binding = true;
if (ofnode_read_u32_array(node, "fixed-link", old_val,
ARRAY_SIZE(old_val))) {
printf("ERROR: no/invalid <fixed-link> property!\n");
return -ENOENT;
}
val = old_val[2];
}
if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000 &&
val != SPEED_2500 && val != SPEED_10000) {
printf("ERROR: no/invalid speed given in fixed-link node!");
printf("ERROR: no/invalid speed given in fixed-link node!\n");
return -EINVAL;
}
@ -38,17 +62,20 @@ int fixedphy_probe(struct phy_device *phydev)
phydev->priv = priv;
priv->link_speed = val;
priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex");
priv->pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "pause");
priv->asym_pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "asym-pause");
/* fixed-link phy must not be reset by core phy code */
phydev->flags |= PHY_FLAG_BROKEN_RESET;
if (!old_binding) {
priv->duplex = ofnode_read_bool(node, "full-duplex");
priv->pause = ofnode_read_bool(node, "pause");
priv->asym_pause = ofnode_read_bool(node, "asym-pause");
} else {
priv->duplex = old_val[1];
priv->pause = old_val[3];
priv->asym_pause = old_val[4];
}
return 0;
}
int fixedphy_startup(struct phy_device *phydev)
static int fixedphy_startup(struct phy_device *phydev)
{
struct fixed_link *priv = phydev->priv;
@ -61,7 +88,7 @@ int fixedphy_startup(struct phy_device *phydev)
return 0;
}
int fixedphy_shutdown(struct phy_device *phydev)
static int fixedphy_shutdown(struct phy_device *phydev)
{
return 0;
}
@ -72,6 +99,7 @@ static struct phy_driver fixedphy_driver = {
.name = "Fixed PHY",
.features = PHY_GBIT_FEATURES | SUPPORTED_MII,
.probe = fixedphy_probe,
.config = fixedphy_config,
.startup = fixedphy_startup,
.shutdown = fixedphy_shutdown,
};

59
drivers/net/phy/phy.c
View File

@ -18,6 +18,7 @@
#include <phy.h>
#include <errno.h>
#include <asm/global_data.h>
#include <dm/of_extra.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
@ -942,34 +943,25 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
}
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
struct udevice *dev,
phy_interface_t interface)
#else
static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
struct eth_device *dev,
phy_interface_t interface)
#endif
{
struct phy_device *phydev = NULL;
int sn = dev_of_offset(dev);
int off;
ofnode node = dev_ofnode(dev);
while (sn > 0) {
off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
"xlnx,gmii-to-rgmii-1.0");
if (off > 0) {
phydev = phy_device_create(bus, off,
while (ofnode_valid(node)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
phydev = phy_device_create(bus, 0,
PHY_GMII2RGMII_ID, false,
interface);
if (phydev)
phydev->node = node;
break;
}
if (off == -FDT_ERR_NOTFOUND)
sn = fdt_first_subnode(gd->fdt_blob, sn);
else
printf("%s: Error finding compat string:%d\n",
__func__, off);
node = ofnode_first_subnode(node);
}
return phydev;
@ -988,6 +980,7 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
struct phy_device *fixed_phy_create(ofnode node)
{
phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
struct phy_device *phydev;
const char *if_str;
ofnode subnode;
@ -1004,33 +997,25 @@ struct phy_device *fixed_phy_create(ofnode node)
return NULL;
}
return phy_device_create(NULL, ofnode_to_offset(subnode), PHY_FIXED_ID,
false, interface);
phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false, interface);
if (phydev)
phydev->node = subnode;
return phydev;
}
#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
struct udevice *dev,
phy_interface_t interface)
#else
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
struct eth_device *dev,
phy_interface_t interface)
#endif
{
ofnode node = dev_ofnode(dev), subnode;
struct phy_device *phydev = NULL;
int sn;
const char *name;
sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
while (sn > 0) {
name = fdt_get_name(gd->fdt_blob, sn, NULL);
if (name && strcmp(name, "fixed-link") == 0) {
phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
interface);
break;
}
sn = fdt_next_subnode(gd->fdt_blob, sn);
if (ofnode_phy_is_fixed_link(node, &subnode)) {
phydev = phy_device_create(bus, 0, PHY_FIXED_ID,
false, interface);
if (phydev)
phydev->node = subnode;
}
return phydev;

61
drivers/net/phy/xilinx_gmii2rgmii.c
View File

@ -18,9 +18,38 @@ DECLARE_GLOBAL_DATA_PTR;
static int xilinxgmiitorgmii_config(struct phy_device *phydev)
{
struct phy_device *ext_phydev = phydev->priv;
ofnode node = phy_get_ofnode(phydev);
struct phy_device *ext_phydev;
struct ofnode_phandle_args phandle;
int ext_phyaddr = -1;
int ret;
debug("%s\n", __func__);
if (!ofnode_valid(node))
return -EINVAL;
phydev->addr = ofnode_read_u32_default(node, "reg", -1);
ret = ofnode_parse_phandle_with_args(node, "phy-handle",
NULL, 0, 0, &phandle);
if (ret)
return ret;
ext_phyaddr = ofnode_read_u32_default(phandle.node, "reg", -1);
ext_phydev = phy_find_by_mask(phydev->bus,
1 << ext_phyaddr,
PHY_INTERFACE_MODE_RGMII);
if (!ext_phydev) {
printf("%s, No external phy device found\n", __func__);
return -EINVAL;
}
ext_phydev->node = phandle.node;
phydev->priv = ext_phydev;
debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr,
ext_phyaddr);
if (ext_phydev->drv->config)
ext_phydev->drv->config(ext_phydev);
@ -83,11 +112,6 @@ static int xilinxgmiitorgmii_startup(struct phy_device *phydev)
static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
{
int ofnode = phydev->addr;
u32 phy_of_handle;
int ext_phyaddr = -1;
struct phy_device *ext_phydev;
debug("%s\n", __func__);
if (phydev->interface != PHY_INTERFACE_MODE_GMII) {
@ -95,31 +119,6 @@ static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
return -EINVAL;
}
/*
* Read the phy address again as the one we read in ethernet driver
* was overwritten for the purpose of storing the ofnode
*/
phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1);
phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode,
"phy-handle");
if (phy_of_handle > 0)
ext_phyaddr = fdtdec_get_int(gd->fdt_blob,
phy_of_handle,
"reg", -1);
ext_phydev = phy_find_by_mask(phydev->bus,
1 << ext_phyaddr,
PHY_INTERFACE_MODE_RGMII);
if (!ext_phydev) {
printf("%s, No external phy device found\n", __func__);
return -EINVAL;
}
ext_phydev->node = offset_to_ofnode(phy_of_handle);
phydev->priv = ext_phydev;
debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr,
ext_phyaddr);
phydev->flags |= PHY_FLAG_BROKEN_RESET;
return 0;

36
drivers/net/tsec.c
View File

@ -707,11 +707,7 @@ static int init_phy(struct tsec_private *priv)
tsec_configure_serdes(priv);
#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
if (ofnode_valid(ofnode_find_subnode(dev_ofnode(priv->dev),
"fixed-link")))
phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
else
phydev = dm_eth_phy_connect(priv->dev);
phydev = dm_eth_phy_connect(priv->dev);
#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
priv->interface);
@ -830,14 +826,40 @@ int tsec_probe(struct udevice *dev)
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct tsec_data *data;
const char *phy_mode;
ofnode parent, child;
fdt_addr_t reg;
ofnode parent;
int ret;
data = (struct tsec_data *)dev_get_driver_data(dev);
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
if (strncmp(ofnode_get_name(child), "queue-group",
strlen("queue-group")))
continue;
reg = ofnode_get_addr(child);
if (reg == FDT_ADDR_T_NONE) {
printf("No 'reg' property of <queue-group>\n");
return -ENOENT;
}
pdata->iobase = reg;
/*
* if there are multiple queue groups,
* only the first one is used.
*/
break;
}
if (!ofnode_valid(child)) {
printf("No child node for <queue-group>?\n");
return -ENOENT;
}
}
priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args);

7
drivers/watchdog/Kconfig
View File

@ -124,6 +124,13 @@ config WDT_BCM6345
The watchdog timer is stopped when initialized.
It performs full SoC reset.
config WDT_BOOKE
bool "PowerPC Book-E watchdog driver"
depends on WDT && MPC85xx
help
Watchdog driver for PowerPC Book-E chips, such as the Freescale
MPC85xx SOCs and the IBM PowerPC 440.
config WDT_CDNS
bool "Cadence watchdog timer support"
depends on WDT

1
drivers/watchdog/Makefile
View File

@ -21,6 +21,7 @@ obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o

106
drivers/watchdog/booke_wdt.c Normal file
View File

@ -0,0 +1,106 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Watchdog timer for PowerPC Book-E systems
*/
#include <div64.h>
#include <dm.h>
#include <wdt.h>
#include <asm/processor.h>
#define WDTP_MASK TCR_WP(0x3f)
/* For the specified period, determine the number of seconds
* corresponding to the reset time. There will be a watchdog
* exception at approximately 3/5 of this time.
*
* The formula to calculate this is given by:
* 2.5 * (2^(63-period+1)) / timebase_freq
*
* In order to simplify things, we assume that period is
* at least 1. This will still result in a very long timeout.
*/
static unsigned long long period_to_sec(unsigned int period)
{
unsigned long long tmp = 1ULL << (64 - period);
unsigned long tmp2 = get_tbclk();
/* tmp may be a very large number and we don't want to overflow,
* so divide the timebase freq instead of multiplying tmp
*/
tmp2 = tmp2 / 5 * 2;
do_div(tmp, tmp2);
return tmp;
}
/*
* This procedure will find the highest period which will give a timeout
* greater than the one required. e.g. for a bus speed of 66666666 and
* and a parameter of 2 secs, then this procedure will return a value of 38.
*/
static unsigned int sec_to_period(unsigned int secs)
{
unsigned int period;
for (period = 63; period > 0; period--) {
if (period_to_sec(period) >= secs)
return period;
}
return 0;
}
static int booke_wdt_reset(struct udevice *dev)
{
mtspr(SPRN_TSR, TSR_ENW | TSR_WIS);
return 0;
}
static int booke_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
u32 val;
unsigned int timeout = DIV_ROUND_UP(timeout_ms, 1000);
/* clear status before enabling watchdog */
booke_wdt_reset(dev);
val = mfspr(SPRN_TCR);
val &= ~WDTP_MASK;
val |= (TCR_WIE | TCR_WRC(WRC_CHIP) | TCR_WP(sec_to_period(timeout)));
mtspr(SPRN_TCR, val);
return 0;
}
static int booke_wdt_stop(struct udevice *dev)
{
u32 val;
val = mfspr(SPRN_TCR);
val &= ~(TCR_WIE | WDTP_MASK);
mtspr(SPRN_TCR, val);
/* clear status to make sure nothing is pending */
booke_wdt_reset(dev);
return 0;
}
static const struct wdt_ops booke_wdt_ops = {
.start = booke_wdt_start,
.stop = booke_wdt_stop,
.reset = booke_wdt_reset,
};
static const struct udevice_id booke_wdt_ids[] = {
{ .compatible = "fsl,booke-wdt" },
{}
};
U_BOOT_DRIVER(booke_wdt) = {
.name = "booke_wdt",
.id = UCLASS_WDT,
.of_match = booke_wdt_ids,
.ops = &booke_wdt_ops,
};

292
include/configs/km/pg-wcom-ls102xa.h Normal file
View File

@ -0,0 +1,292 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
#ifndef __CONFIG_PG_WCOM_LS102XA_H
#define __CONFIG_PG_WCOM_LS102XA_H
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SKIP_LOWLEVEL_INIT
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_SYS_CLK_FREQ 66666666
/*
* Take into account default implementation where DDR_FDBK_MULTI is consider as
* configured for DDR_PLL = 2*MEM_PLL_RAT.
* In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
*/
#define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
/*
* IFC Definitions
*/
/* NOR Flash Definitions */
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_TE | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
CSOR_NOR_ADM_SHIFT(0x4) | \
CSOR_NOR_NOR_MODE_ASYNC_NOR | \
CSOR_NOR_TRHZ_20 | \
CSOR_NOR_BCTLD)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
FTIM0_NOR_TEADC(0x7) | \
FTIM0_NOR_TAVDS(0x0) | \
FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
FTIM1_NOR_TRAD_NOR(0x21) | \
FTIM1_NOR_TSEQRAD_NOR(0x21))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
FTIM2_NOR_TCH(0x1) | \
FTIM2_NOR_TWPH(0x6) | \
FTIM2_NOR_TWP(0xb))
#define CONFIG_SYS_NOR_FTIM3 0
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE 0x68000000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_NAND | \
CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
| CSOR_NAND_ECC_DEC_EN \
| CSOR_NAND_ECC_MODE_4 \
| CSOR_NAND_RAL_3 \
| CSOR_NAND_PGS_2K \
| CSOR_NAND_SPRZ_64 \
| CSOR_NAND_PB(64) \
| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000
#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
#define CONFIG_SYS_CSPR2_EXT (0x00)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_20 | \
CSOR_GPCM_BCTLD)
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
FTIM0_GPCM_TEADC(0x8) | \
FTIM0_GPCM_TEAHC(0x2))
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x6))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
#define CONFIG_SYS_CS2_FTIM3 0x04000000
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/*
* I2C
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_NUM_I2C_BUSES 3
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x0
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{1, {I2C_NULL_HOP} }, \
}
/*
* eTSEC
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME "ethernet@2d90000"
#endif
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CONFIG_FSL_DEVICE_DISABLE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
#define CONFIG_SYS_QE_FW_ADDR 0x60020000
#define CONFIG_SYS_BOOTCOUNT_BE
/*
* Environment
*/
#define CONFIG_ENV_TOTAL_SIZE 0x40000
#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV
#endif
#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
#endif
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize} && " \
"erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
" +${filesize} && " \
"erase " __stringify(CONFIG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
"set_fdthigh=true\0" \
"checkfdt=true\0" \
""
#define CONFIG_KM_NEW_ENV \
"newenv=protect off " __stringify(ENV_DEL_ADDR) \
" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
"erase " __stringify(ENV_DEL_ADDR) \
" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
"protect on " __stringify(ENV_DEL_ADDR) \
" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_NEW_ENV \
CONFIG_KM_DEF_ENV \
"EEprom_ivm=pca9547:70:9\0" \
""
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#endif

2
include/configs/kontron_sl28.h
View File

@ -49,8 +49,6 @@
#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
/* serial port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

7
include/configs/ls1012a2g5rdb.h
View File

@ -61,13 +61,6 @@
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \

7
include/configs/ls1012afrdm.h
View File

@ -47,13 +47,6 @@
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"installer=load usb 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \

7
include/configs/ls1012afrwy.h
View File

@ -80,13 +80,6 @@
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \

7
include/configs/ls1012aqds.h
View File

@ -131,13 +131,6 @@
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \

7
include/configs/ls1012ardb.h
View File

@ -79,13 +79,6 @@
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \

45
include/configs/pg-wcom-seli8.h Normal file
View File

@ -0,0 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
#ifndef __CONFIG_PG_WCOM_SELI8_H
#define __CONFIG_PG_WCOM_SELI8_H
#define CONFIG_HOSTNAME "SELI8"
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* PAXK FPGA Definitions */
#define CONFIG_SYS_CSPR3_EXT (0x00)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define CONFIG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define KM_LIU_RST 0
#define KM_PAXK_RST 1
#define KM_DBG_ETH_RST 15
/* QRIO GPIOs used for deblocking */
#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
#define KM_I2C_DEBLOCK_SCL 20
#define KM_I2C_DEBLOCK_SDA 21
#include "km/pg-wcom-ls102xa.h"
#endif /* __CONFIG_PG_WCOM_SELI8_H */

2
include/configs/sandbox.h
View File

@ -93,7 +93,9 @@
#endif
#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
"eth2addr=00:00:11:22:33:48\0" \
"eth3addr=00:00:11:22:33:45\0" \
"eth4addr=00:00:11:22:33:48\0" \
"eth5addr=00:00:11:22:33:46\0" \
"eth6addr=00:00:11:22:33:47\0" \
"ipaddr=1.2.3.4\0"

20
include/dm/of_extra.h
View File

@ -94,4 +94,24 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type,
const char *suffix, fdt_addr_t *basep,
fdt_size_t *sizep);
/**
* ofnode_phy_is_fixed_link() - Detect fixed-link pseudo-PHY device
*
* This function detects whether the ethernet controller connects to a
* fixed-link pseudo-PHY device.
*
* This function supports the following two DT bindings:
* - the new DT binding, where 'fixed-link' is a sub-node of the
* Ethernet device
* - the old DT binding, where 'fixed-link' is a property with 5
* cells encoding various information about the fixed PHY
*
* If both new and old bindings exist, the new one is preferred.
*
* @param eth_node ofnode containing the fixed-link subnode/property
* @param phy_node if fixed-link PHY detected, containing the PHY ofnode
* @return true if a fixed-link pseudo-PHY device exists, false otherwise
*/
bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node);
#endif

6
include/dm/simple_bus.h
View File

@ -7,9 +7,9 @@
#define __DM_SIMPLE_BUS_H
struct simple_bus_plat {
u32 base;
u32 size;
u32 target;
fdt_addr_t base;
fdt_size_t size;
fdt_addr_t target;
};
#endif

7
net/mdio-uclass.c
View File

@ -11,6 +11,7 @@
#include <miiphy.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/of_extra.h>
#include <dm/uclass-internal.h>
#include <linux/compat.h>
@ -137,11 +138,13 @@ static struct phy_device *dm_eth_connect_phy_handle(struct udevice *ethdev,
struct udevice *mdiodev;
struct phy_device *phy;
struct ofnode_phandle_args phandle = {.node = ofnode_null()};
ofnode phynode;
int i;
if (CONFIG_IS_ENABLED(PHY_FIXED) &&
ofnode_valid(dev_read_subnode(ethdev, "fixed-link"))) {
phy = phy_connect(NULL, -1, ethdev, interface);
ofnode_phy_is_fixed_link(dev_ofnode(ethdev), &phynode)) {
phy = phy_connect(NULL, 0, ethdev, interface);
phandle.node = phynode;
goto out;
}

1
scripts/config_whitelist.txt
View File

@ -1339,7 +1339,6 @@ CONFIG_RESERVED_01_BASE
CONFIG_RESERVED_02_BASE
CONFIG_RESERVED_03_BASE
CONFIG_RESERVED_04_BASE
CONFIG_RESET
CONFIG_RESET_PHY_R
CONFIG_RESET_TO_RETRY
CONFIG_RESET_VECTOR_ADDRESS

2
test/dm/Makefile
View File

@ -29,6 +29,7 @@ obj-$(CONFIG_CLK) += clk.o clk_ccf.o
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-$(CONFIG_DEVRES) += devres.o
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o
obj-$(CONFIG_DM_DSA) += dsa.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_GPIO) += gpio.o
@ -89,6 +90,7 @@ obj-$(CONFIG_DM_MDIO) += mdio.o
obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
obj-$(CONFIG_DM_RNG) += rng.o
obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
obj-$(CONFIG_SIMPLE_BUS) += simple-bus.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o

82
test/dm/dsa.c Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020-2021 NXP Semiconductors
*/
#include <net/dsa.h>
#include <dm/test.h>
#include <test/ut.h>
#include <net.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
/* This test exercises the major dsa.h API functions, after making sure
* that the DSA ports and the master Eth are correctly probed.
*/
static int dm_test_dsa_probe(struct unit_test_state *uts)
{
struct udevice *dev_dsa, *dev_port, *dev_master;
struct dsa_pdata *dsa_pdata;
enum uclass_id id;
id = uclass_get_by_name("dsa");
ut_assert(id == UCLASS_DSA);
ut_assertok(uclass_find_device_by_name(UCLASS_DSA, "dsa-test",
&dev_dsa));
ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test-eth",
&dev_master));
ut_assertok(device_probe(dev_master));
ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@0",
&dev_port));
ut_assertok(device_probe(dev_port));
ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@1",
&dev_port));
ut_assertok(device_probe(dev_port));
/* exercise DSA API */
dsa_pdata = dev_get_uclass_plat(dev_dsa);
ut_assertnonnull(dsa_pdata);
/* includes CPU port */
ut_assert(dsa_pdata->num_ports == 3);
ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan0",
&dev_port));
ut_assertok(device_probe(dev_port));
ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan1",
&dev_port));
ut_assertok(device_probe(dev_port));
dev_master = dsa_get_master(dev_dsa);
ut_assertnonnull(dev_master);
ut_asserteq_str("dsa-test-eth", dev_master->name);
return 0;
}
DM_TEST(dm_test_dsa_probe, UT_TESTF_SCAN_FDT);
/* This test sends ping requests with the local address through each DSA port
* via the sandbox DSA master Eth.
*/
static int dm_test_dsa(struct unit_test_state *uts)
{
net_ping_ip = string_to_ip("1.2.3.5");
env_set("ethact", "eth2");
ut_assertok(net_loop(PING));
env_set("ethact", "lan0");
ut_assertok(net_loop(PING));
env_set("ethact", "lan1");
ut_assertok(net_loop(PING));
env_set("ethact", "");
return 0;
}
DM_TEST(dm_test_dsa, UT_TESTF_SCAN_FDT);

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