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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
30 lines
542 B
Plaintext
30 lines
542 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device tree fragment for RCW SCH-28021 card
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*
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* Copyright 2019-2021 NXP Semiconductors
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*/
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/*
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* SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
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* It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
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* single QSGMII lane.
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* PHY addresses are 0x08 - 0x0b.
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* On the card the first port is the top port (farthest from PEX connector).
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*/
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phy@08 {
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reg = <0x08>;
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};
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phy@09 {
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reg = <0x09>;
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};
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phy@0a {
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reg = <0x0a>;
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};
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phy@0b {
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reg = <0x0b>;
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};
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