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https://github.com/brain-hackers/u-boot-brain
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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
64 lines
1.6 KiB
Plaintext
64 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS1028A-QDS device tree fragment for RCW 9999
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*
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* Copyright 2019-2021 NXP Semiconductors
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*/
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/*
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* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
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* LS1028A QDS boards with lane B rework require two cards for the 4 switch
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* ports, QDS boards without the lane B rework only require one card.
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*
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* Switch ports are routed as follows:
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* Port 0 goes to 1st port of VSC8234 quad card in slot 1,
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* Port 1:
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* - if the QDS has had lane B rework, it is 1st port in slot 2,
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* - otherwise it is 2nd port in slot 1.
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* Port 2:
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* - if DIP SW5[1] = 0 it is 3rd port in slot 1,
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* - otherwise it is 1st port in slot 3.
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* Port 3:
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* - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
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* - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
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* - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
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*
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* The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
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* SCH-24801 cards are required in slots 1 and 2.
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*/
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&slot1 {
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#include "fsl-sch-24801.dtsi"
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};
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&slot2 {
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#include "fsl-sch-24801.dtsi"
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
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};
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&mscc_felix_port1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
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};
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&mscc_felix_port2 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
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};
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&mscc_felix_port3 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
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};
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