Prepare v2021.07-rc3
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This commit is contained in:
Andrey Zhizhikin
commit
44ec13f2c1
2
Kbuild
2
Kbuild
|
|
@ -10,6 +10,8 @@ generic-offsets-file := include/generated/generic-asm-offsets.h
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always := $(generic-offsets-file)
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targets := lib/asm-offsets.s
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CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
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$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
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$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
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|
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24
Kconfig
24
Kconfig
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@ -85,6 +85,30 @@ config SPL_OPTIMIZE_INLINING
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do what it thinks is best, which is desirable in some cases for size
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reasons.
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config ARCH_SUPPORTS_LTO
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bool
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config LTO
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bool "Enable Link Time Optimizations"
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depends on ARCH_SUPPORTS_LTO
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default n
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help
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This option enables Link Time Optimization (LTO), a mechanism which
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allows the compiler to optimize between different compilation units.
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This can optimize away dead code paths, resulting in smaller binary
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size (if CC_OPTIMIZE_FOR_SIZE is enabled).
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This option is not available for every architecture and may
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introduce bugs.
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Currently, when compiling with GCC, due to a weird bug regarding
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jobserver, the final linking will not respect make's --jobs argument.
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Instead all available processors will be used (as reported by the
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nproc command).
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If unsure, say n.
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config TPL_OPTIMIZE_INLINING
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bool "Allow compiler to uninline functions marked 'inline' in TPL"
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depends on TPL
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@ -118,7 +118,7 @@ F: cmd/arm/
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ARM ALTERA SOCFPGA
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M: Marek Vasut <marex@denx.de>
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M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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M: Ley Foon Tan <ley.foon.tan@intel.com>
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M: Ley Foon Tan <lftan.linux@gmail.com>
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S: Maintainted
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T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
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F: arch/arm/mach-socfpga/
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@ -981,6 +981,7 @@ F: arch/powerpc/cpu/mpc86xx/
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RISC-V
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M: Rick Chen <rick@andestech.com>
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M: Leo <ycliang@andestech.com>
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S: Maintained
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T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
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F: arch/riscv/
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101
Makefile
101
Makefile
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@ -3,7 +3,7 @@
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VERSION = 2021
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PATCHLEVEL = 07
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SUBLEVEL =
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EXTRAVERSION = -rc2
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EXTRAVERSION = -rc3
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NAME =
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# *DOCUMENTATION*
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@ -408,7 +408,7 @@ AWK = awk
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PERL = perl
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PYTHON ?= python
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PYTHON2 = python2
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PYTHON3 = python3
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PYTHON3 ?= python3
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DTC ?= $(objtree)/scripts/dtc/dtc
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CHECK = sparse
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@ -676,6 +676,31 @@ else
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KBUILD_CFLAGS += -O2
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endif
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LTO_CFLAGS :=
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LTO_FINAL_LDFLAGS :=
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export LTO_CFLAGS LTO_FINAL_LDFLAGS
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ifdef CONFIG_LTO
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ifeq ($(cc-name),clang)
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LTO_CFLAGS += -flto
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LTO_FINAL_LDFLAGS += -flto
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AR = $(shell $(CC) -print-prog-name=llvm-ar)
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NM = $(shell $(CC) -print-prog-name=llvm-nm)
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else
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NPROC := $(shell nproc 2>/dev/null || echo 1)
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LTO_CFLAGS += -flto=$(NPROC)
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LTO_FINAL_LDFLAGS += -fuse-linker-plugin -flto=$(NPROC)
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|
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# use plugin aware tools
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AR = $(CROSS_COMPILE)gcc-ar
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NM = $(CROSS_COMPILE)gcc-nm
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endif
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|
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CFLAGS_NON_EFI += $(LTO_CFLAGS)
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|
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KBUILD_CFLAGS += $(LTO_CFLAGS)
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endif
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|
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ifeq ($(CONFIG_STACKPROTECTOR),y)
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KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
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CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
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@ -918,6 +943,7 @@ endif
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endif
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INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
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INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
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INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
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ifeq ($(CONFIG_SPL_FRAMEWORK),y)
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INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
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endif
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@ -971,6 +997,8 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL)
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# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
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LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
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LDFLAGS_u-boot += --build-id=none
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ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
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LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
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endif
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@ -1086,10 +1114,8 @@ ifneq ($(CONFIG_DM),y)
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@echo >&2 "See doc/driver-model/migration.rst for more info."
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@echo >&2 "===================================================="
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endif
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$(call deprecated,CONFIG_DM_MMC CONFIG_BLK,MMC,v2019.04,$(CONFIG_MMC))
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$(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
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USB,v2019.07,$(CONFIG_USB))
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$(call deprecated,CONFIG_AHCI,AHCI,v2019.07, $(CONFIG_LIBATA))
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$(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
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$(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\
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$(CONFIG_LCD)$(CONFIG_VIDEO))
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@ -1287,6 +1313,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
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-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
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-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
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-a atf-bl31-path=${BL31} \
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-a opensbi-path=${OPENSBI} \
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-a default-dt=$(default_dt) \
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-a scp-path=$(SCP) \
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-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
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@ -1391,7 +1418,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE
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u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
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$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
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$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
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$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
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,$(UBOOT_BIN)) FORCE
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$(call if_changed,mkimage)
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$(BOARD_SIZE_CHECK)
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@ -1493,10 +1520,16 @@ u-boot.cnt: u-boot.bin FORCE
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flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
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$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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else
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ifeq ($(CONFIG_BINMAN),y)
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flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
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$(call if_changed,binman)
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$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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else
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flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
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$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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endif
|
||||
endif
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||||
endif
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|
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u-boot.uim: u-boot.bin FORCE
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$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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@ -1702,14 +1735,54 @@ u-boot-swap.bin: u-boot.bin FORCE
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|
||||
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
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# Generate linker list symbols references to force compiler to not optimize
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# them away when compiling with LTO
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ifdef CONFIG_LTO
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u-boot-keep-syms-lto := keep-syms-lto.o
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u-boot-keep-syms-lto_c := $(patsubst %.o,%.c,$(u-boot-keep-syms-lto))
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quiet_cmd_keep_syms_lto = KSL $@
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cmd_keep_syms_lto = \
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NM=$(NM) $(srctree)/scripts/gen_ll_addressable_symbols.sh $^ >$@
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quiet_cmd_keep_syms_lto_cc = KSLCC $@
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cmd_keep_syms_lto_cc = \
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$(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
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$(u-boot-keep-syms-lto_c): $(u-boot-main)
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$(call if_changed,keep_syms_lto)
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$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c)
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$(call if_changed,keep_syms_lto_cc)
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else
|
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u-boot-keep-syms-lto :=
|
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endif
|
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|
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# Rule to link u-boot
|
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# May be overridden by arch/$(ARCH)/config.mk
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ifdef CONFIG_LTO
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quiet_cmd_u-boot__ ?= LTO $@
|
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cmd_u-boot__ ?= \
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$(CC) -nostdlib -nostartfiles \
|
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$(LTO_FINAL_LDFLAGS) $(c_flags) \
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$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \
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-T u-boot.lds $(u-boot-init) \
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-Wl,--whole-archive \
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$(u-boot-main) \
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$(u-boot-keep-syms-lto) \
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$(PLATFORM_LIBS) \
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-Wl,--no-whole-archive \
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-Wl,-Map,u-boot.map; \
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$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
|
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else
|
||||
quiet_cmd_u-boot__ ?= LD $@
|
||||
cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
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-T u-boot.lds $(u-boot-init) \
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--start-group $(u-boot-main) --end-group \
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$(PLATFORM_LIBS) -Map u-boot.map; \
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$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
|
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cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
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||||
-T u-boot.lds $(u-boot-init) \
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||||
--whole-archive \
|
||||
$(u-boot-main) \
|
||||
--no-whole-archive \
|
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$(PLATFORM_LIBS) -Map u-boot.map; \
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$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
|
||||
endif
|
||||
|
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quiet_cmd_smap = GEN common/system_map.o
|
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cmd_smap = \
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|
|
@ -1718,7 +1791,7 @@ cmd_smap = \
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$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
|
||||
-c $(srctree)/common/system_map.c -o common/system_map.o
|
||||
|
||||
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
|
||||
u-boot: $(u-boot-init) $(u-boot-main) $(u-boot-keep-syms-lto) u-boot.lds FORCE
|
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+$(call if_changed,u-boot__)
|
||||
ifeq ($(CONFIG_KALLSYMS),y)
|
||||
$(call cmd,smap)
|
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|
|
@ -2001,14 +2074,16 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
|
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boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
|
||||
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
|
||||
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
|
||||
idbloader.img flash.bin flash.log defconfig
|
||||
idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
|
||||
|
||||
# Directories & files removed with 'make mrproper'
|
||||
MRPROPER_DIRS += include/config include/generated spl tpl \
|
||||
.tmp_objdiff doc/output
|
||||
|
||||
# Remove include/asm symlink created by U-Boot before v2014.01
|
||||
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
|
||||
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
|
||||
drivers/video/fonts/*.S
|
||||
drivers/video/fonts/*.S include/asm
|
||||
|
||||
# clean - Delete most, but leave enough to build external modules
|
||||
#
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ config ARC
|
|||
|
||||
config ARM
|
||||
bool "ARM architecture"
|
||||
select ARCH_SUPPORTS_LTO
|
||||
select CREATE_ARCH_SYMLINK
|
||||
select HAVE_PRIVATE_LIBGCC if !ARM64
|
||||
select SUPPORT_OF_CONTROL
|
||||
|
|
@ -101,6 +102,7 @@ config RISCV
|
|||
|
||||
config SANDBOX
|
||||
bool "Sandbox"
|
||||
select ARCH_SUPPORTS_LTO
|
||||
select BOARD_LATE_INIT
|
||||
select BZIP2
|
||||
select CMD_POWEROFF
|
||||
|
|
@ -121,8 +123,10 @@ config SANDBOX
|
|||
select SUPPORT_OF_CONTROL
|
||||
select SYSRESET_CMD_POWEROFF
|
||||
select IRQ
|
||||
select SUPPORT_EXTENSION_SCAN
|
||||
imply BITREVERSE
|
||||
select BLOBLIST
|
||||
imply LTO
|
||||
imply CMD_DM
|
||||
imply CMD_EXCEPTION
|
||||
imply CMD_GETTIME
|
||||
|
|
@ -165,6 +169,7 @@ config SANDBOX
|
|||
imply BOOTARGS_SUBST
|
||||
imply PHY_FIXED
|
||||
imply DM_DSA
|
||||
imply CMD_EXTENSION
|
||||
|
||||
config SH
|
||||
bool "SuperH architecture"
|
||||
|
|
|
|||
|
|
@ -15,9 +15,15 @@ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
|
|||
-fstack-protector-strong
|
||||
CFLAGS_EFI := -fpic -fshort-wchar
|
||||
|
||||
ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
|
||||
LDFLAGS_FINAL += --gc-sections
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
|
||||
-fno-common -ffixed-r9
|
||||
endif
|
||||
|
||||
ifndef CONFIG_LTO
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
|
||||
endif
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-common -ffixed-r9
|
||||
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
|
||||
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@ ifndef CONFIG_HAS_THUMB2
|
|||
|
||||
CFLAGS_cpu.o := -marm
|
||||
CFLAGS_cache.o := -marm
|
||||
CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
|
||||
CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)
|
||||
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/sections.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -98,7 +99,6 @@ int arch_cpu_init(void)
|
|||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
extern uint32_t _start;
|
||||
|
||||
mx28_fixup_vt((uint32_t)&_start);
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/sections.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#include "mxs_init.h"
|
||||
|
|
@ -100,7 +101,6 @@ static void mxs_spl_fixup_vectors(void)
|
|||
* thus this fixup. Our vectoring table is PIC, so copying is
|
||||
* fine.
|
||||
*/
|
||||
extern uint32_t _start;
|
||||
|
||||
/* cppcheck-suppress nullPointer */
|
||||
memcpy(0x0, &_start, 0x60);
|
||||
|
|
@ -122,7 +122,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
|
|||
{
|
||||
struct mxs_spl_data *data = MXS_SPL_DATA;
|
||||
uint8_t bootmode = mxs_get_bootmode_index();
|
||||
gd = &gdata;
|
||||
set_gd(&gdata);
|
||||
|
||||
mxs_spl_fixup_vectors();
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
* The BSS cannot be used for this purpose because it will be zeroed after
|
||||
* having stored the pointer, so force the location to the data section.
|
||||
*/
|
||||
u32 bootrom_stash_sp __attribute__((section(".data")));
|
||||
u32 bootrom_stash_sp __section(".data");
|
||||
|
||||
static void ddr_clock_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
|
||||
int __weak clk_bsc_enable(void *base)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#include <fsl_immap.h>
|
||||
#include "fsl_epu.h"
|
||||
|
||||
#define __secure __attribute__((section("._secure.text")))
|
||||
#define __secure __section("._secure.text")
|
||||
|
||||
#define CCSR_GICD_CTLR 0x1000
|
||||
#define CCSR_GICC_CTLR 0x2000
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@
|
|||
#include <common.h>
|
||||
#include <spl.h>
|
||||
|
||||
char __data_save_start[0] __section(.__data_save_start);
|
||||
char __data_save_end[0] __section(.__data_save_end);
|
||||
char __data_save_start[0] __section(".__data_save_start");
|
||||
char __data_save_end[0] __section(".__data_save_end");
|
||||
|
||||
u32 cold_reboot_flag = 1;
|
||||
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ SECTIONS
|
|||
KEEP(*(.__bss_end));
|
||||
} >.sdram
|
||||
|
||||
/DISCARD/ : { *(.rela*) }
|
||||
/DISCARD/ : { *(.dynsym) }
|
||||
/DISCARD/ : { *(.dynstr*) }
|
||||
/DISCARD/ : { *(.dynamic*) }
|
||||
|
|
|
|||
|
|
@ -237,6 +237,12 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
|
|||
armada-xp-maxbcm.dtb \
|
||||
armada-xp-synology-ds414.dtb \
|
||||
armada-xp-theadorable.dtb \
|
||||
cn9130-db-A.dtb \
|
||||
cn9130-db-B.dtb \
|
||||
cn9131-db-A.dtb \
|
||||
cn9131-db-B.dtb \
|
||||
cn9132-db-A.dtb \
|
||||
cn9132-db-B.dtb \
|
||||
cn9130-crb-A.dtb \
|
||||
cn9130-crb-B.dtb
|
||||
|
||||
|
|
@ -305,6 +311,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
|
|||
zynqmp-mini-emmc1.dtb \
|
||||
zynqmp-mini-nand.dtb \
|
||||
zynqmp-mini-qspi.dtb \
|
||||
zynqmp-sm-k26-revA.dtb \
|
||||
zynqmp-smk-k26-revA.dtb \
|
||||
zynqmp-sck-kv-g-revA.dtbo \
|
||||
zynqmp-sck-kv-g-revB.dtbo \
|
||||
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
|
||||
zynqmp-zcu100-revC.dtb \
|
||||
zynqmp-zcu102-revA.dtb \
|
||||
|
|
@ -811,6 +821,7 @@ dtb-$(CONFIG_ARCH_MX6) += \
|
|||
|
||||
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
|
||||
imx7d-sdb-qspi.dtb \
|
||||
imx7-cm.dtb \
|
||||
imx7-colibri-emmc.dtb \
|
||||
imx7-colibri-rawnand.dtb \
|
||||
imx7s-warp.dtb \
|
||||
|
|
@ -835,6 +846,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
|
|||
|
||||
dtb-$(CONFIG_ARCH_IMX8M) += \
|
||||
imx8mm-evk.dtb \
|
||||
imx8mm-icore-mx8mm-ctouch2.dtb \
|
||||
imx8mm-icore-mx8mm-edimm2.2.dtb \
|
||||
imx8mm-venice.dtb \
|
||||
imx8mm-venice-gw71xx-0x.dtb \
|
||||
imx8mm-venice-gw72xx-0x.dtb \
|
||||
|
|
@ -842,6 +855,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
|
|||
imx8mm-verdin.dtb \
|
||||
phycore-imx8mm.dtb \
|
||||
imx8mn-ddr4-evk.dtb \
|
||||
imx8mq-cm.dtb \
|
||||
imx8mn-evk.dtb \
|
||||
imx8mq-evk.dtb \
|
||||
imx8mm-beacon-kit.dtb \
|
||||
|
|
@ -1056,6 +1070,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
|
|||
k3-j721e-r5-common-proc-board.dtb \
|
||||
k3-j7200-common-proc-board.dtb \
|
||||
k3-j7200-r5-common-proc-board.dtb
|
||||
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
|
||||
k3-am642-r5-evm.dtb \
|
||||
k3-am642-sk.dtb \
|
||||
k3-am642-r5-sk.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
||||
mt7622-rfb.dtb \
|
||||
|
|
@ -1083,6 +1101,8 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
|
|||
|
||||
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
# Add any required device tree compiler flags here
|
||||
|
|
|
|||
|
|
@ -126,14 +126,14 @@
|
|||
ð0 {
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
status = "okay";
|
||||
phy-mode = "sgmii-2500";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
phy = <ðphy0>;
|
||||
};
|
||||
|
||||
ð1 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii-2500";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
phy = <ðphy1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9130 development board (CP NOR) setup(A)";
|
||||
|
||||
aliases {
|
||||
spi0 = &cp0_spi1;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* CP related configuration
|
||||
*/
|
||||
&cp0_pinctl {
|
||||
/* MPP Bus:
|
||||
* [0-11] RGMII1
|
||||
* [12] GPIO GE-IN
|
||||
* [13-16] SPI1
|
||||
* [17-27] NAND
|
||||
* [28] MSS_GPIO[5] XXX:(mode nr from a3900)
|
||||
* [29-30] SATA
|
||||
* [31] MSS_GPIO[4] XXX:(mode nr from a3900)
|
||||
* [32,34] SMI
|
||||
* [33] SDIO
|
||||
* [35-36] I2C1
|
||||
* [37-38] I2C0
|
||||
* [39-43] SDIOctrl
|
||||
* [44-55] RGMII2
|
||||
* [56-62] SDIO
|
||||
*/
|
||||
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 3 3 3 3 3 3 3 3 3 3
|
||||
3 3 0 3 3 3 3 1 1 1
|
||||
1 1 1 1 1 1 1 1 3 9
|
||||
9 3 7 6 7 2 2 2 2 1
|
||||
1 1 1 1 1 1 1 1 1 1
|
||||
1 1 1 1 1 1 0xe 0xe 0xe 0xe
|
||||
0xe 0xe 0xe>;
|
||||
};
|
||||
|
||||
/* U54 */
|
||||
&cp0_nand {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* U55 */
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9130 development board (CP NAND) setup(B)";
|
||||
};
|
||||
|
||||
/*
|
||||
* CP related configuration
|
||||
*/
|
||||
&cp0_pinctl {
|
||||
/* MPP Bus:
|
||||
* [0-11] RGMII1
|
||||
* [12] GPIO GE-IN
|
||||
* [13-14] SPI1
|
||||
* [15-27] NAND
|
||||
* [28] MSS_GPIO[5] XXX:(mode nr from a3900)
|
||||
* [29-30] SATA
|
||||
* [31] MSS_GPIO[4] XXX:(mode nr from a3900)
|
||||
* [32,34] SMI
|
||||
* [33] SDIO
|
||||
* [35-36] I2C1
|
||||
* [37-38] I2C0
|
||||
* [39-43] SDIOctrl
|
||||
* [44-55] RGMII2
|
||||
* [56-62] SDIO
|
||||
*/
|
||||
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 3 3 3 3 3 3 3 3 3 3
|
||||
3 3 0 2 3 1 1 1 1 1
|
||||
1 1 1 1 1 1 1 1 3 9
|
||||
9 3 7 6 7 2 2 2 2 1
|
||||
1 1 1 1 1 1 1 1 1 1
|
||||
1 1 1 1 1 1 0xe 0xe 0xe 0xe
|
||||
0xe 0xe 0xe>;
|
||||
};
|
||||
|
||||
/* U54 */
|
||||
&cp0_nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U55 */
|
||||
&cp0_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
/ {
|
||||
/* This should go only into devel boards */
|
||||
compatible = "marvell,cp110";
|
||||
sar {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sar_fields {
|
||||
compatible = "marvell,sample-at-reset";
|
||||
reg = <0x4c 0x4e>;
|
||||
chip_count = <2>;
|
||||
bit_width = <5>;
|
||||
freq {
|
||||
key = "freq";
|
||||
description = "CPU/DDR and PIDI frequencies";
|
||||
start-bit = <0>;
|
||||
bit-length = <4>;
|
||||
option-cnt = <3>;
|
||||
options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz",
|
||||
"0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz",
|
||||
"0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz";
|
||||
default = <0x2>;
|
||||
status = "okay";
|
||||
};
|
||||
boot_mode {
|
||||
key = "boot_mode";
|
||||
description = "Boot mode options";
|
||||
start-bit = <4>;
|
||||
bit-length = <6>;
|
||||
option-cnt = <4>;
|
||||
options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)",
|
||||
"0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)",
|
||||
"0x2A", "AP_EMMC",
|
||||
"0x32", "CP1_SPI_1 24bits";
|
||||
default = <0x32>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,316 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130.dtsi" /* include SoC device tree */
|
||||
#include "cn9130-db-dev-info.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DB-CN-9130";
|
||||
compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
"marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = &cp0_i2c0;
|
||||
gpio0 = &ap_gpio0;
|
||||
gpio1 = &cp0_gpio0;
|
||||
gpio2 = &cp0_gpio1;
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
cp0 {
|
||||
config-space {
|
||||
i2c@701000 {
|
||||
/* U36 */
|
||||
expander0: pca953x@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
sdhci@780000 {
|
||||
vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
};
|
||||
|
||||
ap_reg_mmc_vccq: ap_mmc_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "ap_mmc_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <100000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <100000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0_sd_vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microamp = <900000>;
|
||||
regulator-max-microamp = <900000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microamp = <900000>;
|
||||
regulator-max-microamp = <900000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&expander0 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* AP related configuration
|
||||
*/
|
||||
&ap_pinctl {
|
||||
/* MPP Bus:
|
||||
* SDIO [0-10, 12]
|
||||
* UART0 [11,19]
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 1 1 1 1 1 1 1 1 1 1
|
||||
1 3 1 0 0 0 0 0 0 3 >;
|
||||
};
|
||||
|
||||
/* on-board eMMC - U9 */
|
||||
&ap_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ap_emmc_pins>;
|
||||
vqmmc-supply = <&ap_reg_mmc_vccq>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* CP related configuration
|
||||
*/
|
||||
&cp0_pinctl {
|
||||
cp0_nand_pins: cp0-nand-pins {
|
||||
marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >;
|
||||
marvell,function = <1>;
|
||||
};
|
||||
cp0_nand_rb: cp0-nand-rb {
|
||||
marvell,pins = < 13 >;
|
||||
marvell,function = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* CP0
|
||||
*/
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON 28 */
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U54 */
|
||||
&cp0_nand {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* U55 */
|
||||
&cp0_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi0_pins>;
|
||||
reg = <0x700680 0x50>, /* control */
|
||||
<0x2000000 0x1000000>, /* CS0 */
|
||||
<0 0xffffffff>, /* CS1 */
|
||||
<0 0xffffffff>, /* CS2 */
|
||||
<0 0xffffffff>; /* CS3 */
|
||||
status = "disabled";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor", "spi-flash";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_comphy {
|
||||
phy0 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy1 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy2 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy3 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy4 {
|
||||
phy-type = <COMPHY_TYPE_SFI0>;
|
||||
phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
};
|
||||
|
||||
phy5 {
|
||||
phy-type = <COMPHY_TYPE_SATA1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp0_pcie0 {
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "sfi";
|
||||
};
|
||||
|
||||
/* CON56 */
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON57 */
|
||||
&cp0_eth2 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON2 */
|
||||
&cp0_sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
vbus-supply = <&cp0_reg_usb3_vbus0>;
|
||||
current-limiter = <&cp0_reg_usb3_current_lim0>;
|
||||
vbus-disable-delay = <500>;
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
vbus-supply = <&cp0_reg_usb3_vbus1>;
|
||||
current-limiter = <&cp0_reg_usb3_current_lim1>;
|
||||
vbus-disable-delay = <500>;
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-db-A.dts"
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9131 development board (CP NOR) setup(A)";
|
||||
compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&cp1_comphy {
|
||||
/* Serdes Configuration:
|
||||
* Lane 0: PCIe0 (x2)
|
||||
* Lane 1: PCIe0 (x2)
|
||||
* Lane 2: unconnected
|
||||
* Lane 3: USB1
|
||||
* Lane 4: SFP (port 0)
|
||||
* Lane 5: SATA1
|
||||
*/
|
||||
phy0 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
phy1 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
phy2 {
|
||||
phy-type = <COMPHY_TYPE_UNCONNECTED>;
|
||||
};
|
||||
phy3 {
|
||||
phy-type = <COMPHY_TYPE_USB3_HOST1>;
|
||||
};
|
||||
phy4 {
|
||||
phy-type = <COMPHY_TYPE_SFI0>;
|
||||
phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
};
|
||||
phy5 {
|
||||
phy-type = <COMPHY_TYPE_SATA1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON50 */
|
||||
&cp1_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "sfi"; /* lane-4 */
|
||||
marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-db-B.dts"
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9131 development board (CP NAND) setup(B)";
|
||||
compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&cp1_comphy {
|
||||
/* Serdes Configuration:
|
||||
* Lane 0: PCIe0 (x2)
|
||||
* Lane 1: PCIe0 (x2)
|
||||
* Lane 2: SFI (port 0)
|
||||
* Lane 3: USB1
|
||||
* Lane 4: SGMII (port 1)
|
||||
* Lane 5: SATA1
|
||||
*/
|
||||
phy0 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
phy1 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
phy2 {
|
||||
phy-type = <COMPHY_TYPE_SFI0>;
|
||||
phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
};
|
||||
phy3 {
|
||||
phy-type = <COMPHY_TYPE_USB3_HOST1>;
|
||||
};
|
||||
phy4 {
|
||||
phy-type = <COMPHY_TYPE_SGMII1>;
|
||||
phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
};
|
||||
phy5 {
|
||||
phy-type = <COMPHY_TYPE_SATA1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* 3310 RJ45 CON55 */
|
||||
&cp1_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "sfi"; /* lane-2 */
|
||||
phy = <&sfi_phy8>; /* required by 3310 fw download */
|
||||
};
|
||||
|
||||
/* CON50 */
|
||||
&cp1_eth1 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii"; /* lane-4 */
|
||||
marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&cp1_xmdio {
|
||||
status = "okay";
|
||||
sfi_phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#undef CP110_NAME
|
||||
#undef CP110_NUM
|
||||
#undef CP110_PCIE_MEM_SIZE
|
||||
#undef CP110_PCIEx_CPU_MEM_BASE
|
||||
#undef CP110_PCIEx_BUS_MEM_BASE
|
||||
|
||||
/* CP110-1 Settings */
|
||||
#define CP110_NAME cp1
|
||||
#define CP110_NUM 1
|
||||
#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
|
||||
#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
|
||||
#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
|
||||
|
||||
#include "armada-cp110.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9131 development board";
|
||||
compatible = "marvell,cn9131-db";
|
||||
|
||||
aliases {
|
||||
gpio3 = &cp1_gpio0;
|
||||
gpio4 = &cp1_gpio1;
|
||||
};
|
||||
|
||||
cp1 {
|
||||
config-space {
|
||||
cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_xhci0_vbus_pins>;
|
||||
regulator-name = "cp1-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <100000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microamp = <900000>;
|
||||
regulator-max-microamp = <900000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
cp1_pcie_reset_pins: cp1-pcie-reset-pins {
|
||||
marvell,pins = <0>;
|
||||
marvell,function = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* CON40 */
|
||||
&cp1_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_pcie_reset_pins>;
|
||||
marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
num-lanes = <2>;
|
||||
/* non-prefetchable memory */
|
||||
ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
|
||||
};
|
||||
|
||||
&cp1_pinctl {
|
||||
compatible = "marvell,mvebu-pinctrl",
|
||||
"marvell,cp115-standalone-pinctrl";
|
||||
bank-name ="cp1-110";
|
||||
|
||||
/* MPP Bus:
|
||||
* [0-12] GPIO
|
||||
* [13-16] SPI1
|
||||
* [17-27] GPIO (Default)
|
||||
* [28] SATA1_PRESENT_ACTIVEn
|
||||
* [29-34] GPIO (Default)
|
||||
* [35-36] xSMI
|
||||
* [37-38] I2C0
|
||||
* [39-62] GPIO
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 >;
|
||||
|
||||
cp1_i2c0_pins: cp1-i2c-pins-0 {
|
||||
marvell,pins = < 37 38 >;
|
||||
marvell,function = <2>;
|
||||
};
|
||||
cp1_spi0_pins: cp1-spi-pins-0 {
|
||||
marvell,pins = < 13 14 15 16 >;
|
||||
marvell,function = <3>;
|
||||
};
|
||||
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
|
||||
marvell,pins = <3>;
|
||||
marvell,function = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON32 */
|
||||
&cp1_sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U24 */
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi0_pins>;
|
||||
reg = <0x700680 0x50>, /* control */
|
||||
<0x2000000 0x1000000>, /* CS0 */
|
||||
<0 0xffffffff>, /* CS1 */
|
||||
<0 0xffffffff>, /* CS2 */
|
||||
<0 0xffffffff>; /* CS3 */
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor", "spi-flash";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON58 */
|
||||
&cp1_usb3_1 {
|
||||
vbus-supply = <&cp1_reg_usb3_vbus0>;
|
||||
current-limiter = <&cp1_reg_usb3_current_lim0>;
|
||||
vbus-disable-delay = <500>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_utmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9131-db-A.dts"
|
||||
#include "cn9132-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9132 development board (CP NOR) setup(A)";
|
||||
compatible = "marvell,cn9132-db", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9131-db-B.dts"
|
||||
#include "cn9132-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9132 development board (CP NAND) setup(B)";
|
||||
compatible = "marvell,cn9132-db-B", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#undef CP110_NAME
|
||||
#undef CP110_NUM
|
||||
#undef CP110_PCIE_MEM_SIZE
|
||||
#undef CP110_PCIEx_CPU_MEM_BASE
|
||||
#undef CP110_PCIEx_BUS_MEM_BASE
|
||||
|
||||
/* CP110-2 Settings */
|
||||
#define CP110_NAME cp2
|
||||
#define CP110_NUM 2
|
||||
#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
|
||||
#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
|
||||
#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
|
||||
|
||||
#include "armada-cp110.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell CN9132 development board";
|
||||
compatible = "marvell,cn9132-db";
|
||||
|
||||
aliases {
|
||||
gpio5 = &cp2_gpio0;
|
||||
gpio6 = &cp2_gpio1;
|
||||
};
|
||||
|
||||
cp2 {
|
||||
config-space {
|
||||
sdhci@780000 {
|
||||
vqmmc-supply = <&cp2_reg_sd_vccq>;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <100000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp2_gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <100000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp2_gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
cp2_reg_sd_vccq: cp2_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp2_sd_vcc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
/* cp2_mpp49 */
|
||||
gpios = <&cp2_gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
cp2_reg_usb3_current_lim0: cp2_usb3_current_limiter@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microamp = <900000>;
|
||||
regulator-max-microamp = <900000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp2_gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_current_lim1: cp2_usb3_current_limiter@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microamp = <900000>;
|
||||
regulator-max-microamp = <900000>;
|
||||
regulator-force-boot-off;
|
||||
gpio = <&cp2_gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&cp2_pinctl {
|
||||
compatible = "marvell,mvebu-pinctrl",
|
||||
"marvell,cp115-standalone-pinctrl";
|
||||
bank-name ="cp2-110";
|
||||
|
||||
/* MPP Bus:
|
||||
* [0-26] GPIO
|
||||
* [27] SATA0_PRESENT_ACTIVEn
|
||||
* [28] SATA1_PRESENT_ACTIVEn
|
||||
* [29-31, 33] GPIO (Default)
|
||||
* [32,34] SMI
|
||||
* [37-38] I2C0
|
||||
* [39-53] GPIO
|
||||
* [54] SD_CRD_RSTn (out)
|
||||
* [55] SD_CRD_DT (in)
|
||||
* [56-62] SDIO
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x0
|
||||
0x0 0x0 0x8 0x0 0x8 0x0 0x0 0x2 0x2 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0xa 0xb 0xe 0xe 0xe 0xe
|
||||
0xe 0xe 0xe >;
|
||||
|
||||
cp2_i2c0_pins: cp2-i2c-pins-0 {
|
||||
marvell,pins = < 37 38 >;
|
||||
marvell,function = <2>;
|
||||
};
|
||||
|
||||
cp2_sdhci_pins: cp2-sdhi-pins-0 {
|
||||
marvell,pins = < 56 57 58 59 60 61 >;
|
||||
marvell,function = <14>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_usb3_0 {
|
||||
status = "okay";
|
||||
vbus-supply = <&cp2_reg_usb3_vbus0>;
|
||||
current-limiter = <&cp2_reg_usb3_current_lim0>;
|
||||
vbus-disable-delay = <500>;
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON11 */
|
||||
&cp2_usb3_1 {
|
||||
status = "okay";
|
||||
vbus-supply = <&cp2_reg_usb3_vbus1>;
|
||||
current-limiter = <&cp2_reg_usb3_current_lim1>;
|
||||
vbus-disable-delay = <500>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_utmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_utmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_comphy {
|
||||
phy0 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy1 {
|
||||
phy-type = <COMPHY_TYPE_PEX0>;
|
||||
};
|
||||
|
||||
phy2 {
|
||||
phy-type = <COMPHY_TYPE_SATA0>;
|
||||
};
|
||||
|
||||
phy3 {
|
||||
phy-type = <COMPHY_TYPE_USB3_HOST1>;
|
||||
};
|
||||
|
||||
phy4 {
|
||||
phy-type = <COMPHY_TYPE_SFI0>;
|
||||
phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
};
|
||||
|
||||
phy5 {
|
||||
phy-type = <COMPHY_TYPE_PEX2>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp2_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "sfi";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp2_pcie0 {
|
||||
/* non-prefetchable memory */
|
||||
ranges =<0x82000000 0 0xe5000000 0 0xe5000000 0 0x1000000>;
|
||||
num-lanes = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON8 */
|
||||
&cp2_pcie2 {
|
||||
num-lanes = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_pinctl {
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON4 */
|
||||
&cp2_sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON 2 on SLM-1683 - microSD */
|
||||
&cp2_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_sdhci_pins>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -35,3 +35,15 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* This is not done in imx6q-ba16.dtsi, since that file is shared
|
||||
* with the kernel and the kernel should not reset the PHY, since
|
||||
* it lacks support for configuring the reserved registeres to
|
||||
* avoid a board specific voltage peak issue.
|
||||
*/
|
||||
&fec {
|
||||
phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <1>;
|
||||
phy-reset-post-delay = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -120,7 +120,6 @@
|
|||
regulator-name = "5P0V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
/{
|
||||
aliases {
|
||||
mmc0 = &usdhc1;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_i2c1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
//
|
||||
// Copyright 2021 Ronetix GmbH
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx7d.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ronetix iMX7-CM Board";
|
||||
compatible = "ronetix,imx7-cm", "fsl,imx7d";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
/* DRAM size runtime extracted from the DDRC registers */
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
led {
|
||||
label = "gpio-led";
|
||||
gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_sd1_vmmc: regulator-sd1-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_SD1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <200000>;
|
||||
off-on-delay-us = <20000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1_pwr>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg2_pwr>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
|
||||
<&clks IMX7D_CLKO2_ROOT_DIV>;
|
||||
assigned-clock-parents = <&clks IMX7D_CKIL>;
|
||||
assigned-clock-rates = <0>, <32768>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi1_1>;
|
||||
status = "okay";
|
||||
ddrsmp=<0>;
|
||||
|
||||
flash0: mx25l25645g@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@8 {
|
||||
compatible = "fsl,pfuze3000";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1a {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
/* use sw1c_reg to align with pfuze100/pfuze200 */
|
||||
sw1c_reg: sw1b {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vldo2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen3_reg: vccsd {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: v33 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vldo3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vldo4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_otg2_vbus>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
tuning-step = <2>;
|
||||
vmmc-supply = <®_sd1_vmmc>;
|
||||
wakeup-source;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
bus-width = <8>;
|
||||
no-1-8-v;
|
||||
fsl,tuning-step = <2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
|
||||
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
|
||||
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
|
||||
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* ETH_RESET */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x59
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x59
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_pwr: usbotg_pwr {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg2_pwr: usbotg_pwr {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 /* CD */
|
||||
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* Vmmc */
|
||||
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi1_1: qspi1grp_1 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
|
||||
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
|
||||
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
|
||||
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
|
||||
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
|
||||
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc_lpsr {
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,6 +3,8 @@
|
|||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
|
|
@ -11,32 +13,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
|
@ -65,15 +41,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pca6416_0 {
|
||||
compatible = "ti,tca6416";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,255 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/ {
|
||||
binman: binman {
|
||||
multiple-images;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdog1>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_uart3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2_gpio {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_i2c2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_pmic {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&binman {
|
||||
u-boot-spl-ddr {
|
||||
filename = "u-boot-spl-ddr.bin";
|
||||
pad-byte = <0xff>;
|
||||
align-size = <4>;
|
||||
align = <4>;
|
||||
|
||||
u-boot-spl {
|
||||
align-end = <4>;
|
||||
};
|
||||
|
||||
blob_1: blob-ext@1 {
|
||||
filename = "lpddr4_pmu_train_1d_imem.bin";
|
||||
size = <0x8000>;
|
||||
};
|
||||
|
||||
blob_2: blob-ext@2 {
|
||||
filename = "lpddr4_pmu_train_1d_dmem.bin";
|
||||
size = <0x4000>;
|
||||
};
|
||||
|
||||
blob_3: blob-ext@3 {
|
||||
filename = "lpddr4_pmu_train_2d_imem.bin";
|
||||
size = <0x8000>;
|
||||
};
|
||||
|
||||
blob_4: blob-ext@4 {
|
||||
filename = "lpddr4_pmu_train_2d_dmem.bin";
|
||||
size = <0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
flash {
|
||||
mkimage {
|
||||
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
|
||||
|
||||
blob {
|
||||
filename = "u-boot-spl-ddr.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
itb {
|
||||
filename = "u-boot.itb";
|
||||
|
||||
fit {
|
||||
description = "Configuration to load ATF before U-Boot";
|
||||
#address-cells = <1>;
|
||||
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
|
||||
|
||||
images {
|
||||
uboot {
|
||||
description = "U-Boot (64-bit)";
|
||||
type = "standalone";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <CONFIG_SYS_TEXT_BASE>;
|
||||
|
||||
uboot_blob: blob-ext {
|
||||
filename = "u-boot-nodtb.bin";
|
||||
};
|
||||
};
|
||||
|
||||
atf {
|
||||
description = "ARM Trusted Firmware";
|
||||
type = "firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <0x920000>;
|
||||
entry = <0x920000>;
|
||||
|
||||
atf_blob: blob-ext {
|
||||
filename = "bl31.bin";
|
||||
};
|
||||
};
|
||||
|
||||
fip {
|
||||
description = "Trusted Firmware FIP";
|
||||
type = "firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <0x40310000>;
|
||||
|
||||
fip_blob: blob-ext{
|
||||
filename = "fip.bin";
|
||||
};
|
||||
};
|
||||
|
||||
fdt {
|
||||
description = "NAME";
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
|
||||
uboot_fdt_blob: blob-ext {
|
||||
filename = "u-boot.dtb";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
default = "conf";
|
||||
|
||||
conf {
|
||||
description = "NAME";
|
||||
firmware = "uboot";
|
||||
loadables = "atf", "fip";
|
||||
fdt = "fdt";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,553 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CompuLab IOT-GATE-iMX8";
|
||||
compatible = "sb-iotgimx8", "cpl,ucm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200";
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
|
||||
reg_vusb_5v: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VUSB_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usdhc2_vqmmc: regulator-usdhc2_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usdhc2_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <100>;
|
||||
off-on-delay-us = <12000>;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
at803x,led-act-blind-workaround;
|
||||
at803x,eee-okay;
|
||||
at803x,vddio-1p8v;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
rtc@69 {
|
||||
compatible = "abracon,ab1805";
|
||||
reg = <0x69>;
|
||||
pagesize = <16>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71837";
|
||||
reg = <0x4b>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
gpo {
|
||||
rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
|
||||
};
|
||||
|
||||
regulators {
|
||||
bd71837,pmic-buck2-uses-i2c-dvs;
|
||||
bd71837,pmic-buck2-dvs-voltage = <1000000>,
|
||||
<900000>,
|
||||
<0>; /* VDD_ARM: Run-Idle */
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "BUCK3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "BUCK7";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "BUCK8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "LDO7";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptn5110: tcpc@50 {
|
||||
compatible = "nxp,ptn5110";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_typec1>;
|
||||
reg = <0x50>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 8>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
typec1_dr_sw: endpoint {
|
||||
remote-endpoint = <&usb1_drd_sw>;
|
||||
};
|
||||
};
|
||||
|
||||
typec1_con: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
try-power-role = "sink";
|
||||
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
|
||||
PDO_VAR(5000, 20000, 3000)>;
|
||||
op-sink-microwatt = <15000000>;
|
||||
self-powered;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c4 {/* Expansion connector I2C */
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
|
||||
pca9555: gpio@22 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "host";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
vbus-supply = <®_vusb_5v>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usb1_drd_sw: endpoint {
|
||||
remote-endpoint = <&typec1_dr_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
fsl,wp-controller;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
no-1-8-v;
|
||||
mmc-ddr-1_8v;
|
||||
non-removable;
|
||||
vqmmc-supply = <®_usdhc2_vqmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* USB VBUS enable GPIO */
|
||||
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_1: hoggrp-1 {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
|
||||
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
|
||||
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
|
||||
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
|
||||
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
|
||||
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirq {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec1: typec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
|
||||
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
|
||||
MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
|
||||
MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
|
||||
MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,6 +3,8 @@
|
|||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
binman: binman {
|
||||
multiple-images;
|
||||
|
|
@ -22,41 +24,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
®_usdhc2_vmmc {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include "imx8mm-icore-mx8mm-u-boot.dtsi"
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_gpio {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 NXP
|
||||
* Copyright (c) 2019 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx8mm.dtsi"
|
||||
#include "imx8mm-icore-mx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";
|
||||
compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
|
||||
"fsl,imx8mm";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
||||
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
pm-ignore-notify;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include "imx8mm-icore-mx8mm-u-boot.dtsi"
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_gpio {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 NXP
|
||||
* Copyright (c) 2019 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx8mm.dtsi"
|
||||
#include "imx8mm-icore-mx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
|
||||
compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
|
||||
"fsl,imx8mm";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
||||
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
pm-ignore-notify;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3_100mhz {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3_200mhz {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 NXP
|
||||
* Copyright (c) 2019 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <®_buck4>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <®_buck4>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <®_buck4>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <®_buck4>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@8 {
|
||||
compatible = "nxp,pf8121a";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
reg_ldo1: ldo1 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_ldo2: ldo2 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_ldo3: ldo3 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_ldo4: ldo4 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck1: buck1 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck2: buck2 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck3: buck3 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck4: buck4 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck5: buck5 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck6: buck6 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_buck7: buck7 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_vsnvs: vsnvs {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -3,40 +3,7 @@
|
|||
* Copyright 2021 Gateworks Corporation
|
||||
*/
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@
|
|||
* Copyright 2021 Gateworks Corporation
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
|
|
@ -11,41 +13,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,6 +2,9 @@
|
|||
/*
|
||||
* Copyright 2020 Toradex
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
|
|
@ -10,27 +13,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -55,15 +37,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl_i2c1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -84,11 +57,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,111 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/ {
|
||||
binman: binman {
|
||||
multiple-images;
|
||||
};
|
||||
};
|
||||
|
||||
&binman {
|
||||
u-boot-spl-ddr {
|
||||
filename = "u-boot-spl-ddr.bin";
|
||||
pad-byte = <0xff>;
|
||||
align-size = <4>;
|
||||
align = <4>;
|
||||
|
||||
u-boot-spl {
|
||||
align-end = <4>;
|
||||
};
|
||||
|
||||
blob_1: blob-ext@1 {
|
||||
filename = "lpddr4_pmu_train_1d_imem.bin";
|
||||
size = <0x8000>;
|
||||
};
|
||||
|
||||
blob_2: blob-ext@2 {
|
||||
filename = "lpddr4_pmu_train_1d_dmem.bin";
|
||||
size = <0x4000>;
|
||||
};
|
||||
|
||||
blob_3: blob-ext@3 {
|
||||
filename = "lpddr4_pmu_train_2d_imem.bin";
|
||||
size = <0x8000>;
|
||||
};
|
||||
|
||||
blob_4: blob-ext@4 {
|
||||
filename = "lpddr4_pmu_train_2d_dmem.bin";
|
||||
size = <0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
flash {
|
||||
mkimage {
|
||||
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
|
||||
|
||||
blob {
|
||||
filename = "u-boot-spl-ddr.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
itb {
|
||||
filename = "u-boot.itb";
|
||||
|
||||
fit {
|
||||
description = "Configuration to load ATF before U-Boot";
|
||||
#address-cells = <1>;
|
||||
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
|
||||
|
||||
images {
|
||||
uboot {
|
||||
description = "U-Boot (64-bit)";
|
||||
type = "standalone";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <CONFIG_SYS_TEXT_BASE>;
|
||||
|
||||
uboot_blob: blob-ext {
|
||||
filename = "u-boot-nodtb.bin";
|
||||
};
|
||||
};
|
||||
|
||||
atf {
|
||||
description = "ARM Trusted Firmware";
|
||||
type = "firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <0x910000>;
|
||||
entry = <0x910000>;
|
||||
|
||||
atf_blob: blob-ext {
|
||||
filename = "bl31.bin";
|
||||
};
|
||||
};
|
||||
|
||||
fdt {
|
||||
description = "NAME";
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
|
||||
uboot_fdt_blob: blob-ext {
|
||||
filename = "u-boot.dtb";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
default = "conf";
|
||||
|
||||
conf {
|
||||
description = "NAME";
|
||||
firmware = "uboot";
|
||||
loadables = "atf";
|
||||
fdt = "fdt";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,535 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2021 Ronetix, Ilko Iliev <iliev@ronetix.at>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mq.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ronetix iMX8M-CM SoM";
|
||||
compatible = "ronetix,imx8mq-cm", "fsl,imx8mq";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pmic_osc: clock-pmic {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "pmic_osc";
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-25M {
|
||||
opp-hz = /bits/ 64 <25000000>;
|
||||
};
|
||||
|
||||
opp-100M {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* On imx8mq B0 PLL can't be bypassed so low bus is 166M
|
||||
*/
|
||||
opp-166M {
|
||||
opp-hz = /bits/ 64 <166935483>;
|
||||
};
|
||||
|
||||
opp-800M {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71837";
|
||||
reg = <0x4b>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc_32k 0>;
|
||||
clock-output-names = "clk-32k-out";
|
||||
|
||||
regulators {
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
rohm,dvs-run-voltage = <1000000>;
|
||||
rohm,dvs-idle-voltage = <900000>;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
// BUCK5 in datasheet
|
||||
regulator-name = "buck3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
||||
regulator-name = "buck4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "buck5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "buck7";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "buck8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "ldo6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c_eeprom: i2c_eeprom@50 {
|
||||
compatible = "microchip,24lc512";
|
||||
reg = <0x50>;
|
||||
pagesize = <128>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MQ_CLK_PCIE1_PHY>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_gpu {
|
||||
power-supply = <&buck3_reg>;
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
|
||||
mx25l51245g: flash@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vqmmc-supply = <&buck7_reg>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_buck2: vddarmgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067
|
||||
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
|
||||
MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 /* PMIC intr */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
|
||||
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2: regusdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,567 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_main {
|
||||
oc_sram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x70000000 0x00 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x70000000 0x200000>;
|
||||
|
||||
atf-sram@0 {
|
||||
reg = <0x0 0x1a000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01840000 0x00 0xC0000>; /* GICR */
|
||||
/*
|
||||
* vcpumntirq:
|
||||
* virtual CPU interface maintenance interrupt
|
||||
*/
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gic_its: msi-controller@1820000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
dmss: dmss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges;
|
||||
ranges;
|
||||
|
||||
ti,sci-dev-id = <25>;
|
||||
|
||||
secure_proxy_main: mailbox@4d000000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x4d000000 0x00 0x80000>,
|
||||
<0x00 0x4a600000 0x00 0x80000>,
|
||||
<0x00 0x4a400000 0x00 0x80000>;
|
||||
interrupt-names = "rx_012";
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
inta_main_dmss: interrupt-controller@48000000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x00 0x48000000 0x00 0x100000>;
|
||||
#interrupt-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <28>;
|
||||
ti,interrupt-ranges = <4 68 36>;
|
||||
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
|
||||
};
|
||||
|
||||
main_bcdma: dma-controller@485c0100 {
|
||||
compatible = "ti,am64-dmss-bcdma";
|
||||
reg = <0x00 0x485c0100 0x00 0x100>,
|
||||
<0x00 0x4c000000 0x00 0x20000>,
|
||||
<0x00 0x4a820000 0x00 0x20000>,
|
||||
<0x00 0x4aa40000 0x00 0x20000>,
|
||||
<0x00 0x4bc00000 0x00 0x100000>;
|
||||
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <3>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <26>;
|
||||
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
|
||||
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
|
||||
};
|
||||
|
||||
main_pktdma: dma-controller@485c0000 {
|
||||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <30>;
|
||||
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
|
||||
<0x24>, /* CPSW_TX_CHAN */
|
||||
<0x25>, /* SAUL_TX_0_CHAN */
|
||||
<0x26>, /* SAUL_TX_1_CHAN */
|
||||
<0x27>, /* ICSSG_0_TX_CHAN */
|
||||
<0x28>; /* ICSSG_1_TX_CHAN */
|
||||
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
|
||||
<0x11>, /* RING_CPSW_TX_CHAN */
|
||||
<0x12>, /* RING_SAUL_TX_0_CHAN */
|
||||
<0x13>, /* RING_SAUL_TX_1_CHAN */
|
||||
<0x14>, /* RING_ICSSG_0_TX_CHAN */
|
||||
<0x15>; /* RING_ICSSG_1_TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
|
||||
<0x2b>, /* CPSW_RX_CHAN */
|
||||
<0x2d>, /* SAUL_RX_0_CHAN */
|
||||
<0x2f>, /* SAUL_RX_1_CHAN */
|
||||
<0x31>, /* SAUL_RX_2_CHAN */
|
||||
<0x33>, /* SAUL_RX_3_CHAN */
|
||||
<0x35>, /* ICSSG_0_RX_CHAN */
|
||||
<0x37>; /* ICSSG_1_RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
|
||||
<0x2c>, /* FLOW_CPSW_RX_CHAN */
|
||||
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
|
||||
<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
|
||||
<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
|
||||
<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
|
||||
};
|
||||
};
|
||||
|
||||
dmsc: dmsc@44043000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes= <&secure_proxy_main 12>,
|
||||
<&secure_proxy_main 13>;
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44043000 0x00 0xfe0>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinctrl@f4000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x00 0xf4000 0x00 0x2d0>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_conf: syscon@43000000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x43000000 0x20000>;
|
||||
|
||||
chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x00000014 0x4>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4044 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4044 0x8>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 146 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 152 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 153 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 154 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 155 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 156 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 158 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_i2c0: i2c@20000000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20000000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 102 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c1: i2c@20010000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20010000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 103 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c2: i2c@20020000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20020000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 104 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 141 0>;
|
||||
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
|
||||
dma-names = "tx0", "rx0";
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 142 0>;
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 143 0>;
|
||||
};
|
||||
|
||||
main_spi3: spi@20130000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20130000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 144 0>;
|
||||
};
|
||||
|
||||
main_spi4: spi@20140000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20140000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 145 0>;
|
||||
};
|
||||
|
||||
sdhci0: mmc@fa10000 {
|
||||
compatible = "ti,am64-sdhci-8bit";
|
||||
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x7>;
|
||||
ti,otap-del-sel-hs400 = <0x4>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am64-sdhci-4bit";
|
||||
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x8000000 0x0 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 1>;
|
||||
assigned-clock-parents = <&k3_clks 13 9>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_pktdma 0xC500 15>,
|
||||
<&main_pktdma 0xC501 15>,
|
||||
<&main_pktdma 0xC502 15>,
|
||||
<&main_pktdma 0xC503 15>,
|
||||
<&main_pktdma 0xC504 15>,
|
||||
<&main_pktdma 0xC505 15>,
|
||||
<&main_pktdma 0xC506 15>,
|
||||
<&main_pktdma 0xC507 15>,
|
||||
<&main_pktdma 0x4500 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 de ad be ef];
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 01 de ad be ef];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x0 0xf00 0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x3d000 0x0 0x400>;
|
||||
clocks = <&k3_clks 13 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00600000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 77 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00601000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 78 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_i2c0: i2c@20000000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x20000000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 102 2>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c1: i2c@20010000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x20010000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 103 2>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c2: i2c@20020000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20020000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 104 2>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 105 2>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 160 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04900000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@4910000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04910000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM642 SoC";
|
||||
compatible = "ti,am642";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &mcu_uart0;
|
||||
serial1 = &mcu_uart1;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
i2c0 = &main_i2c0;
|
||||
i2c1 = &main_i2c1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f4000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
|
||||
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
|
||||
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
|
||||
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
|
||||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
||||
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
||||
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am64-main.dtsi"
|
||||
#include "k3-am64-mcu.dtsi"
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
timer1: timer@2400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x2400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <250000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
u-boot,dm-spl;
|
||||
chipid@14 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
reg = <0x0 0x8000000 0x0 0x200000>,
|
||||
<0x0 0x43000200 0x0 0x8>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@04044 {
|
||||
compatible = "ti,am64-phy-gmii-sel";
|
||||
reg = <0x0 0x43004044 0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,339 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
model = "Texas Instruments AM642 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main DC jack */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: fixedregulator-vsys5v0 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixed-regulator-sd {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vddb: fixedregulator-vddb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddb_3v3_display";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "am64-evm:red:heartbeat";
|
||||
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mdio_mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mdio-mux-1 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mdio_mux>;
|
||||
mdio-parent-bus = <&cpsw3g_mdio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
&main_uart1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
|
||||
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
|
||||
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
|
||||
"MMC1_SD_EN", "FSI_FET_SEL",
|
||||
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
|
||||
"CPSW_FET_SEL", "CPSW_FET2_SEL",
|
||||
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
|
||||
"GPIO_OLED_RESETn", "VPP_LDO_EN",
|
||||
"TEST_LED1", "TP92", "TP90", "TP88",
|
||||
"TP87", "TP86", "TP89", "TP91";
|
||||
};
|
||||
|
||||
/* osd9616p0899-10 */
|
||||
display@3c {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
|
||||
vbat-supply = <&vddb>;
|
||||
solomon,height = <16>;
|
||||
solomon,width = <96>;
|
||||
solomon,com-seq;
|
||||
solomon,com-invdir;
|
||||
solomon,page-offset = <0>;
|
||||
solomon,prechargep1 = <2>;
|
||||
solomon,prechargep2 = <13>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* emmc */
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am642.dtsi"
|
||||
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
|
||||
#include "k3-am64-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
a53_0: a53@0 {
|
||||
compatible = "ti,am654-rproc";
|
||||
reg = <0x00 0x00a90000 0x00 0x10>;
|
||||
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
|
||||
resets = <&k3_reset 135 0>;
|
||||
clocks = <&k3_clks 61 0>;
|
||||
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 61 2>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-proc-id = <32>;
|
||||
ti,sci-host-id = <10>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clk_200mhz: dummy-clock-200mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
vtt_supply: vtt-supply {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <0>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
states = <0 0x0 3300000 0x1>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
|
||||
mbox-names = "tx", "rx";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
ddr_vtt_pins_default: ddr-vtt-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
<&secure_proxy_main 0>;
|
||||
mbox-names = "rx", "tx", "notify";
|
||||
ti,host-id = <35>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ clock-names;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&memorycontroller {
|
||||
vtt-supply = <&vtt_supply>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ddr_vtt_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
u-boot,dm-spl;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
/* EEPROM might be read before SYSFW is available */
|
||||
&main_i2c0 {
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
#include "k3-am642-evm-u-boot.dtsi"
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am642.dtsi"
|
||||
#include "k3-am64-sk-lp4-1333MTs.dtsi"
|
||||
#include "k3-am64-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
a53_0: a53@0 {
|
||||
compatible = "ti,am654-rproc";
|
||||
reg = <0x00 0x00a90000 0x00 0x10>;
|
||||
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
|
||||
resets = <&k3_reset 135 0>;
|
||||
clocks = <&k3_clks 61 0>;
|
||||
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 61 2>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-proc-id = <32>;
|
||||
ti,sci-host-id = <10>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clk_200mhz: dummy-clock-200mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
|
||||
mbox-names = "tx", "rx";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
<&secure_proxy_main 0>;
|
||||
mbox-names = "rx", "tx", "notify";
|
||||
ti,host-id = <35>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ clock-names;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
};
|
||||
|
||||
#include "k3-am642-sk-u-boot.dtsi"
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
timer1: timer@2400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x2400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <250000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
u-boot,dm-spl;
|
||||
chipid@14 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
reg = <0x0 0x8000000 0x0 0x200000>,
|
||||
<0x0 0x43000200 0x0 0x8>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@04044 {
|
||||
compatible = "ti,am64-phy-gmii-sel";
|
||||
reg = <0x0 0x43004044 0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
model = "Texas Instruments AM642 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC family in Dual core configuration
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am64.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include "meson-g12-common-u-boot.dtsi"
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include "meson-g12-common-u-boot.dtsi"
|
||||
|
|
@ -4,6 +4,8 @@
|
|||
* Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
*/
|
||||
|
||||
#include "imx8mm-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
|
|
@ -12,41 +14,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&{/soc@0} {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&clk {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&osc_24m {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips1 {
|
||||
u-boot,dm-spl;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&aips2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_uart3 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* dts file for Xilinx Versal a2197 RevA System Controller
|
||||
*
|
||||
* (C) Copyright 2019 - 2020, Xilinx, Inc.
|
||||
* (C) Copyright 2019 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
|
@ -163,20 +163,20 @@
|
|||
"", "", "", "", "", /* 70 - 74 */
|
||||
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
|
||||
"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 - 89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
|
||||
"SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
|
||||
"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
|
||||
"SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
|
||||
"MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
|
|
@ -457,6 +457,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c-mux-idle-disconnect;
|
||||
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
dc_i2c: i2c@0 { /* DC_I2C */
|
||||
#address-cells = <1>;
|
||||
|
|
@ -475,6 +476,7 @@
|
|||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "ref_clk";
|
||||
silabs,skip-recall;
|
||||
};
|
||||
/* and connector J212D */
|
||||
};
|
||||
|
|
@ -504,6 +506,7 @@
|
|||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_ddrdimm1_clk";
|
||||
silabs,skip-recall;
|
||||
};
|
||||
};
|
||||
i2c@4 { /* LPDDR4_SI570_CLK2 */
|
||||
|
|
@ -559,6 +562,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c-mux-idle-disconnect;
|
||||
i2c@0 { /* SFP0_IIC */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -343,9 +343,10 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
silabs,skip-recall;
|
||||
};
|
||||
/* Connection via Samtec U20D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
|
|
|
|||
|
|
@ -349,9 +349,10 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
silabs,skip-recall;
|
||||
};
|
||||
/* Connection via Samtec U20D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
|
|
|
|||
|
|
@ -339,9 +339,10 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
silabs,skip-recall;
|
||||
};
|
||||
/* Connection via Samtec U20D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,46 @@
|
|||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
#power-domain-cells = <1>;
|
||||
method = "smc";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
zynqmp_power: zynqmp-power {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
mboxes = <&ipi_mailbox_pmu1 0>,
|
||||
<&ipi_mailbox_pmu1 1>;
|
||||
mbox-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
zynqmp_ipi: zynqmp_ipi {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "xlnx,zynqmp-ipi-mailbox";
|
||||
xlnx,ipi-id = <0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ipi_mailbox_pmu1: mailbox@ff990400 {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0x0 0xff9905c0 0x0 0x20>,
|
||||
<0x0 0xff9905e0 0x0 0x20>,
|
||||
<0x0 0xff990e80 0x0 0x20>,
|
||||
<0x0 0xff990ea0 0x0 0x20>;
|
||||
reg-names = "local_request_region",
|
||||
"local_response_region",
|
||||
"remote_request_region",
|
||||
"remote_response_region";
|
||||
#mbox-cells = <1>;
|
||||
xlnx,ipi-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,46 @@
|
|||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
#power-domain-cells = <1>;
|
||||
method = "smc";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
zynqmp_power: zynqmp-power {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
mboxes = <&ipi_mailbox_pmu1 0>,
|
||||
<&ipi_mailbox_pmu1 1>;
|
||||
mbox-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
zynqmp_ipi: zynqmp_ipi {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "xlnx,zynqmp-ipi-mailbox";
|
||||
xlnx,ipi-id = <0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ipi_mailbox_pmu1: mailbox@ff990400 {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0x0 0xff9905c0 0x0 0x20>,
|
||||
<0x0 0xff9905e0 0x0 0x20>,
|
||||
<0x0 0xff990e80 0x0 0x20>,
|
||||
<0x0 0xff990ea0 0x0 0x20>;
|
||||
reg-names = "local_request_region",
|
||||
"local_response_region",
|
||||
"remote_request_region",
|
||||
"remote_response_region";
|
||||
#mbox-cells = <1>;
|
||||
xlnx,ipi-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
|
||||
|
|
@ -43,6 +44,18 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
si5332_1: si5332_1 { /* clk0_sgmii - u142 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <33333333>; /* FIXME */
|
||||
};
|
||||
|
||||
si5332_2: si5332_2 { /* clk1_usb - u142 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
|
||||
|
|
@ -70,6 +83,13 @@
|
|||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* sgmii, usb3 */
|
||||
clocks = <&si5332_1>, <&si5332_2>;
|
||||
clock-names = "ref0", "ref1";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
|
|
@ -390,6 +410,7 @@
|
|||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "ref_clk";
|
||||
silabs,skip-recall;
|
||||
};
|
||||
/* Connection via Samtec J212D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
|
|
@ -536,6 +557,8 @@
|
|||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
maximum-speed = "super-speed";
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,373 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for KV260 revA Carrier Card
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* SD level shifter:
|
||||
* "A" – A01 board un-modified (NXP)
|
||||
* "Y" – A01 board modified with legacy interposer (Nexperia)
|
||||
* "Z" – A01 board modified with Diode interposer
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/{
|
||||
compatible = "xlnx,zynqmp-sk-kv260-revA",
|
||||
"xlnx,zynqmp-sk-kv260-revY",
|
||||
"xlnx,zynqmp-sk-kv260-revZ",
|
||||
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
|
||||
|
||||
fragment1 {
|
||||
target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
u14: ina260@40 { /* u14 */
|
||||
compatible = "ti,ina260";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina260-u14";
|
||||
reg = <0x40>;
|
||||
};
|
||||
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
|
||||
};
|
||||
};
|
||||
|
||||
fragment1a {
|
||||
target = <&amba>;
|
||||
__overlay__ {
|
||||
ina260-u14 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
|
||||
};
|
||||
|
||||
si5332_0: si5332_0 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
si5332_1: si5332_1 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
si5332_2: si5332_2 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
si5332_3: si5332_3 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
si5332_4: si5332_4 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
si5332_5: si5332_5 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* DP/USB 3.0 and SATA */
|
||||
fragment2 {
|
||||
target = <&psgtr>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
/* pcie, usb3, sata */
|
||||
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
|
||||
clock-names = "ref0", "ref1", "ref2";
|
||||
};
|
||||
};
|
||||
|
||||
fragment3 {
|
||||
target = <&sata>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment4 {
|
||||
target = <&zynqmp_dpsub>;
|
||||
__overlay__ {
|
||||
status = "disabled";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment9 {
|
||||
target = <&zynqmp_dpdma>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment10 {
|
||||
target = <&usb0>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
usbhub: usb5744 { /* u43 */
|
||||
compatible = "microchip,usb5744";
|
||||
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment11 {
|
||||
target = <&dwc3_0>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
};
|
||||
|
||||
fragment12 {
|
||||
target = <&sdhci1>; /* on CC with tuned parameters */
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
/*
|
||||
* SD 3.0 requires level shifter and this property
|
||||
* should be removed if the board has level shifter and
|
||||
* need to work in UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment13 {
|
||||
target = <&gem3>; /* required by spec */
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment14 {
|
||||
target = <&pinctrl0>; /* required by spec */
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
conf {
|
||||
groups = "uart1_9_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO37";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO36";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "uart1_9_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
conf {
|
||||
groups = "i2c1_6_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "i2c1_6_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
conf {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO72", "MIO74";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-bootstrap {
|
||||
pins = "MIO71", "MIO73", "MIO75";
|
||||
bias-disable;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66",
|
||||
"MIO67", "MIO68", "MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
fragment15 {
|
||||
target = <&uart1>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for KV260 revA Carrier Card
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/{
|
||||
compatible = "xlnx,zynqmp-sk-kv260-rev1",
|
||||
"xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
|
||||
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
|
||||
|
||||
fragment1 {
|
||||
target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
u14: ina260@40 { /* u14 */
|
||||
compatible = "ti,ina260";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina260-u14";
|
||||
reg = <0x40>;
|
||||
};
|
||||
usbhub: usb5744@2d { /* u43 */
|
||||
compatible = "microchip,usb5744";
|
||||
reg = <0x2d>;
|
||||
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
|
||||
};
|
||||
};
|
||||
|
||||
fragment1a {
|
||||
target = <&amba>;
|
||||
__overlay__ {
|
||||
ina260-u14 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
|
||||
};
|
||||
|
||||
si5332_0: si5332_0 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
si5332_1: si5332_1 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
si5332_2: si5332_2 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
si5332_3: si5332_3 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
si5332_4: si5332_4 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
si5332_5: si5332_5 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* DP/USB 3.0 */
|
||||
fragment2 {
|
||||
target = <&psgtr>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
/* pcie, usb3, sata */
|
||||
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
|
||||
clock-names = "ref0", "ref1", "ref2";
|
||||
};
|
||||
};
|
||||
|
||||
fragment4 {
|
||||
target = <&zynqmp_dpsub>;
|
||||
__overlay__ {
|
||||
status = "disabled";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment9 {
|
||||
target = <&zynqmp_dpdma>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment10 {
|
||||
target = <&usb0>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment11 {
|
||||
target = <&dwc3_0>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
};
|
||||
|
||||
fragment12 {
|
||||
target = <&sdhci1>; /* on CC with tuned parameters */
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
/*
|
||||
* SD 3.0 requires level shifter and this property
|
||||
* should be removed if the board has level shifter and
|
||||
* need to work in UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio-bank = <1>;
|
||||
clk-phase-sd-hs = <126>, <60>;
|
||||
clk-phase-uhs-sdr25 = <120>, <60>;
|
||||
clk-phase-uhs-ddr50 = <126>, <48>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment13 {
|
||||
target = <&gem3>; /* required by spec */
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment14 {
|
||||
target = <&pinctrl0>; /* required by spec */
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
conf {
|
||||
groups = "uart1_9_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO37";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO36";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "uart1_9_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
conf {
|
||||
groups = "i2c1_6_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "i2c1_6_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
conf {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO72", "MIO74";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-bootstrap {
|
||||
pins = "MIO71", "MIO73", "MIO75";
|
||||
bias-disable;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66",
|
||||
"MIO67", "MIO68", "MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
fragment15 {
|
||||
target = <&uart1>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP K26/KV260 SD wiring
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/* SD0 only supports 3.3V, no level shifter */
|
||||
&sdhci1 { /* on CC - MIO 39 - 51 */
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
broken-cd;
|
||||
xlnx,mio-bank = <1>;
|
||||
/* Do not run SD in HS mode from bootloader */
|
||||
sdhci-caps-mask = <0 0x200000>;
|
||||
sdhci-caps = <0 0>;
|
||||
max-frequency = <19000000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,316 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SM-K26 Rev1/B/A";
|
||||
compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
|
||||
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
|
||||
"xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
spi1 = &spi0;
|
||||
spi2 = &spi1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
nvmem0 = &eeprom;
|
||||
nvmem1 = &eeprom_cc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory"; /* 4GB */
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
fwuen {
|
||||
label = "fwuen";
|
||||
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
ds35 {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds36 {
|
||||
label = "vbus_det";
|
||||
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
ams {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
|
||||
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
|
||||
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
|
||||
<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
|
||||
<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
|
||||
<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
|
||||
<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
|
||||
<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
|
||||
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
|
||||
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 { /* MIO36/MIO37 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi { /* MIO 0-5 - U143 */
|
||||
status = "okay";
|
||||
flash@0 { /* MT25QU512A */
|
||||
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <40000000>; /* 40MHz */
|
||||
partition@0 {
|
||||
label = "Image Selector";
|
||||
reg = <0x0 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "Image Selector Golden";
|
||||
reg = <0x80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "Persistent Register";
|
||||
reg = <0x100000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@120000 {
|
||||
label = "Persistent Register Backup";
|
||||
reg = <0x120000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@140000 {
|
||||
label = "Open_1";
|
||||
reg = <0x140000 0xC0000>; /* 768KB */
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Image A (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0x200000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "ImgSel Image A Catch";
|
||||
reg = <0xF00000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@f80000 {
|
||||
label = "Image B (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0xF80000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@1c80000 {
|
||||
label = "ImgSel Image B Catch";
|
||||
reg = <0x1C80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@1d00000 {
|
||||
label = "Open_2";
|
||||
reg = <0x1D00000 0x100000>; /* 1MB */
|
||||
};
|
||||
partition@1e00000 {
|
||||
label = "Recovery Image";
|
||||
reg = <0x1E00000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2000000 {
|
||||
label = "Recovery Image Backup";
|
||||
reg = <0x2000000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2200000 {
|
||||
label = "U-Boot storage variables";
|
||||
reg = <0x2200000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2220000 {
|
||||
label = "U-Boot storage variables backup";
|
||||
reg = <0x2220000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2240000 {
|
||||
label = "SHA256";
|
||||
reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2250000 {
|
||||
label = "User";
|
||||
reg = <0x2250000 0x1db0000>; /* 29.5 MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/
|
||||
status = "okay";
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&spi1 { /* MIO6, 9-11 */
|
||||
status = "okay";
|
||||
label = "TPM";
|
||||
num-cs = <1>;
|
||||
tpm@0 { /* slm9670 - U144 */
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <18500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x50>;
|
||||
/* WP pin EE_WP_EN connected to slg7x644092@68 */
|
||||
};
|
||||
|
||||
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
/* da9062@30 - u170 - also at address 0x31 */
|
||||
/* da9131@33 - u167 */
|
||||
da9131: pmic@33 {
|
||||
compatible = "dlg,da9131";
|
||||
reg = <0x33>;
|
||||
regulators {
|
||||
da9131_buck1: buck1 {
|
||||
regulator-name = "da9131_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
da9131_buck2: buck2 {
|
||||
regulator-name = "da9131_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* da9130@32 - u166 */
|
||||
da9130: pmic@32 {
|
||||
compatible = "dlg,da9130";
|
||||
reg = <0x32>;
|
||||
regulators {
|
||||
da9130_buck1: buck1 {
|
||||
regulator-name = "da9130_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
|
||||
/*
|
||||
* stdp4320 - u27 FW has below two issues to be fixed in next board revision.
|
||||
* Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
|
||||
* Address conflict with slg7x644091@70 making both the devices NOT accessible.
|
||||
* With the FW fix, stdp4320 should respond to address 0x73 only.
|
||||
*/
|
||||
/* slg7x644092@68 - u169 */
|
||||
/* Also connected via JA1C as C23/C24 */
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
|
||||
"QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
|
||||
"SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
|
||||
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
|
||||
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
|
||||
"I2C1_SDA", "", "", "", "", /* 25 - 29 */
|
||||
"", "", "", "", "", /* 30 - 34 */
|
||||
"", "", "", "", "", /* 35 - 39 */
|
||||
"", "", "", "", "", /* 40 - 44 */
|
||||
"", "", "", "", "", /* 45 - 49 */
|
||||
"", "", "", "", "", /* 50 - 54 */
|
||||
"", "", "", "", "", /* 55 - 59 */
|
||||
"", "", "", "", "", /* 60 - 64 */
|
||||
"", "", "", "", "", /* 65 - 69 */
|
||||
"", "", "", "", "", /* 70 - 74 */
|
||||
"", "", "", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 - 89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP Z2-VSOM
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/* SD0 only supports 3.3V, no level shifter */
|
||||
&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
broken-cd;
|
||||
xlnx,mio-bank = <1>;
|
||||
/* Do not run SD in HS mode from bootloader */
|
||||
sdhci-caps-mask = <0 0x200000>;
|
||||
sdhci-caps = <0 0>;
|
||||
max-frequency = <19000000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
|
||||
*
|
||||
* (C) Copyright 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-sm-k26-revA.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SMK-K26 Rev1/B/A";
|
||||
compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
|
||||
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
|
||||
"xlnx,zynqmp";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -11,6 +11,9 @@
|
|||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm015-dc1 RevA";
|
||||
|
|
@ -37,6 +40,31 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
clock_si5338_0: clk27 { /* u55 SI5338-GM */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
clock_si5338_2: clk26 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
clock_si5338_3: clk150 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <150000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* dp, usb3, sata */
|
||||
clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
|
|
@ -75,6 +103,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -82,6 +112,8 @@
|
|||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
|
|
@ -91,6 +123,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
eeprom: eeprom@55 {
|
||||
compatible = "atmel,24c64"; /* 24AA64 */
|
||||
|
|
@ -98,6 +135,216 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_9_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_9_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_36_grp", "gpio0_37_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_36_grp", "gpio0_37_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_8_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_8_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO34";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO35";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_0_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
function = "sdio0_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_38_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
|
|
@ -142,11 +389,15 @@
|
|||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
bus-width = <8>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
|
@ -158,21 +409,30 @@
|
|||
* This property should be removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm016-dc2 RevA";
|
||||
|
|
@ -43,10 +45,14 @@
|
|||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can0_default>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
|
|
@ -85,6 +91,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem2_default>;
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -101,6 +109,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u26: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -118,6 +131,8 @@
|
|||
|
||||
&nand0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand0_default>;
|
||||
arasan,has-mdma;
|
||||
|
||||
nand@0 {
|
||||
|
|
@ -190,6 +205,285 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_can0_default: can0-default {
|
||||
mux {
|
||||
function = "can0";
|
||||
groups = "can0_9_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can0_9_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO38";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO39";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_8_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_8_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO33";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO32";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_1_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_1_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_6_grp", "gpio0_7_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_6_grp", "gpio0_7_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_10_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_10_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO42";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO43";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_10_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_10_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO41";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO40";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb1_default: usb1-default {
|
||||
mux {
|
||||
groups = "usb1_0_grp";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem2_default: gem2-default {
|
||||
mux {
|
||||
function = "ethernet2";
|
||||
groups = "ethernet2_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet2_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
|
||||
"MIO63";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
|
||||
"MIO57";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio2";
|
||||
groups = "mdio2_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio2_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_nand0_default: nand0-default {
|
||||
mux {
|
||||
groups = "nand0_0_grp";
|
||||
function = "nand0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "nand0_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-ce {
|
||||
groups = "nand0_ce_0_grp";
|
||||
function = "nand0_ce";
|
||||
};
|
||||
|
||||
conf-ce {
|
||||
groups = "nand0_ce_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-rb {
|
||||
groups = "nand0_rb_0_grp";
|
||||
function = "nand0_rb";
|
||||
};
|
||||
|
||||
conf-rb {
|
||||
groups = "nand0_rb_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-dqs {
|
||||
groups = "nand0_dqs_0_grp";
|
||||
function = "nand0_dqs";
|
||||
};
|
||||
|
||||
conf-dqs {
|
||||
groups = "nand0_dqs_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi0_default: spi0-default {
|
||||
mux {
|
||||
groups = "spi0_0_grp";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi0_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
|
||||
"spi0_ss_2_grp";
|
||||
function = "spi0_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
|
||||
"spi0_ss_2_grp";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi1_default: spi1-default {
|
||||
mux {
|
||||
groups = "spi1_3_grp";
|
||||
function = "spi1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi1_3_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
|
||||
"spi1_ss_11_grp";
|
||||
function = "spi1_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
|
||||
"spi1_ss_11_grp";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -197,6 +491,9 @@
|
|||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0_default>;
|
||||
|
||||
spi0_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -214,6 +511,9 @@
|
|||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1_default>;
|
||||
|
||||
spi1_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -231,6 +531,8 @@
|
|||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1_default>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
|
|
@ -240,8 +542,12 @@
|
|||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,6 +12,9 @@
|
|||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm019-dc5 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
|
@ -73,6 +76,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem1_default>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -84,41 +89,366 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_18_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_18_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_74_grp", "gpio0_75_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_74_grp", "gpio0_75_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_19_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_19_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_76_grp", "gpio0_77_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_76_grp", "gpio0_77_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_17_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO71";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_18_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_18_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO73";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO72";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem1_default: gem1-default {
|
||||
mux {
|
||||
function = "ethernet1";
|
||||
groups = "ethernet1_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
|
||||
"MIO49";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
|
||||
"MIO43";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio1";
|
||||
groups = "mdio1_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_0_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
function = "sdio0_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_watchdog0_default: watchdog0-default {
|
||||
mux-clk {
|
||||
groups = "swdt0_clk_1_grp";
|
||||
function = "swdt0_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "swdt0_clk_1_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-rst {
|
||||
groups = "swdt0_rst_1_grp";
|
||||
function = "swdt0_rst";
|
||||
};
|
||||
|
||||
conf-rst {
|
||||
groups = "swdt0_rst_1_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc0_default: ttc0-default {
|
||||
mux-clk {
|
||||
groups = "ttc0_clk_0_grp";
|
||||
function = "ttc0_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc0_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc0_wav_0_grp";
|
||||
function = "ttc0_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc0_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc1_default: ttc1-default {
|
||||
mux-clk {
|
||||
groups = "ttc1_clk_0_grp";
|
||||
function = "ttc1_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc1_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc1_wav_0_grp";
|
||||
function = "ttc1_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc1_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc2_default: ttc2-default {
|
||||
mux-clk {
|
||||
groups = "ttc2_clk_0_grp";
|
||||
function = "ttc2_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc2_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc2_wav_0_grp";
|
||||
function = "ttc2_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc2_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc3_default: ttc3-default {
|
||||
mux-clk {
|
||||
groups = "ttc3_clk_0_grp";
|
||||
function = "ttc3_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc3_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc3_wav_0_grp";
|
||||
function = "ttc3_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc3_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&ttc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc0_default>;
|
||||
};
|
||||
|
||||
&ttc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc1_default>;
|
||||
};
|
||||
|
||||
&ttc2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc2_default>;
|
||||
};
|
||||
|
||||
&ttc3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc3_default>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_watchdog0_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -185,6 +186,11 @@
|
|||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
clock-frequency = <100000>;
|
||||
i2c-mux@75 { /* u11 */
|
||||
compatible = "nxp,pca9548";
|
||||
|
|
@ -262,6 +268,221 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_1_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_1_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_4_grp", "gpio0_5_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_4_grp", "gpio0_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_3_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_3_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_2_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_2_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi0_default: spi0-default {
|
||||
mux {
|
||||
groups = "spi0_3_grp";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi0_3_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi0_ss_9_grp";
|
||||
function = "spi0_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi0_ss_9_grp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pinctrl_spi1_default: spi1-default {
|
||||
mux {
|
||||
groups = "spi1_0_grp";
|
||||
function = "spi1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi1_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi1_ss_0_grp";
|
||||
function = "spi1_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi1_ss_0_grp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_0_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO3";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO2";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_0_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO1";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb1_default: usb1-default {
|
||||
mux {
|
||||
groups = "usb1_0_grp";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* usb3, dps */
|
||||
|
|
@ -278,12 +499,16 @@
|
|||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
bus-width = <0x4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <0>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
|
@ -304,16 +529,22 @@
|
|||
status = "okay";
|
||||
label = "LS-SPI0";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0_default>;
|
||||
};
|
||||
|
||||
&spi1 { /* High Speed connector */
|
||||
status = "okay";
|
||||
label = "HS-SPI1";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1_default>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
bluetooth {
|
||||
compatible = "ti,wl1831-st";
|
||||
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
|
|
@ -322,28 +553,37 @@
|
|||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1_default>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -154,6 +155,8 @@
|
|||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -196,6 +199,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -208,6 +213,8 @@
|
|||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
|
|
@ -217,6 +224,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -476,6 +488,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
|
|
@ -658,6 +675,269 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux-sw {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf-sw {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22", "MIO23";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -726,26 +1006,36 @@
|
|||
* removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -62,6 +63,8 @@
|
|||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -104,6 +107,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -124,6 +129,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
|
|
@ -215,6 +225,204 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
|
|
@ -274,27 +482,37 @@
|
|||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -68,6 +69,8 @@
|
|||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -110,6 +113,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -130,6 +135,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -228,6 +238,204 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
|
|
@ -287,27 +495,37 @@
|
|||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -154,6 +155,8 @@
|
|||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -208,6 +211,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -219,6 +224,8 @@
|
|||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
|
|
@ -228,6 +235,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -486,6 +498,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
|
|
@ -678,6 +695,269 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO23", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
|
|
@ -741,26 +1021,36 @@
|
|||
* This property should be removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -170,6 +171,8 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
|
|
@ -181,6 +184,8 @@
|
|||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
|
|
@ -190,6 +195,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u22: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -365,6 +375,11 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
i2c-mux@74 { /* u26 */
|
||||
compatible = "nxp,pca9548";
|
||||
|
|
@ -554,6 +569,210 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO23", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
|
|
@ -607,12 +826,14 @@
|
|||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
disable-wp;
|
||||
/*
|
||||
* This property should be removed for supporting UHS mode
|
||||
|
|
@ -623,12 +844,23 @@
|
|||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -221,6 +222,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u15: gpio@20 { /* u15 */
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -382,12 +388,18 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548"; /* u20 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c-mux-idle-disconnect;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c_eeprom: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -423,27 +435,27 @@
|
|||
si5341_2: out@2 {
|
||||
/* refclk2 for PS-GT, used for USB3 */
|
||||
reg = <2>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_3: out@3 {
|
||||
/* refclk3 for PS-GT, used for SATA */
|
||||
reg = <3>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_5: out@5 {
|
||||
/* refclk5 PL CLK100 */
|
||||
reg = <5>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_6: out@6 {
|
||||
/* refclk6 PL CLK125 */
|
||||
reg = <6>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_9: out@9 {
|
||||
/* refclk9 used for PS_REF_CLK 33.3 MHz */
|
||||
reg = <9>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -504,6 +516,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c-mux-idle-disconnect;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -565,6 +578,63 @@
|
|||
/* MSP430 */
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
|
|
@ -601,6 +671,7 @@
|
|||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
|
|
@ -628,4 +699,6 @@
|
|||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -232,6 +233,11 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u15: gpio@20 { /* u15 */
|
||||
compatible = "ti,tca6416";
|
||||
|
|
@ -393,12 +399,18 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548"; /* u20 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c-mux-idle-disconnect;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c_eeprom: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -434,27 +446,27 @@
|
|||
si5341_2: out@2 {
|
||||
/* refclk2 for PS-GT, used for USB3 */
|
||||
reg = <2>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_3: out@3 {
|
||||
/* refclk3 for PS-GT, used for SATA */
|
||||
reg = <3>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_5: out@5 {
|
||||
/* refclk5 PL CLK100 */
|
||||
reg = <5>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_6: out@6 {
|
||||
/* refclk6 PL CLK125 */
|
||||
reg = <6>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
si5341_9: out@9 {
|
||||
/* refclk9 used for PS_REF_CLK 33.3 MHz */
|
||||
reg = <9>;
|
||||
always-on; /* assigned-clocks does not enable, so do it here */
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -515,6 +527,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c-mux-idle-disconnect;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -576,6 +589,63 @@
|
|||
/* MSP430 */
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
|
|
@ -605,6 +675,7 @@
|
|||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
|
|
@ -632,4 +703,6 @@
|
|||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ struct arch_global_data {
|
|||
|
||||
#include <asm-generic/global_data.h>
|
||||
|
||||
#ifdef __clang__
|
||||
#if defined(__clang__) || defined(CONFIG_LTO)
|
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR
|
||||
#define gd get_gd()
|
||||
|
|
@ -122,8 +122,10 @@ static inline void set_gd(volatile gd_t *gd_ptr)
|
|||
{
|
||||
#ifdef CONFIG_ARM64
|
||||
__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
|
||||
#else
|
||||
#elif __ARM_ARCH >= 7
|
||||
__asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
|
||||
#else
|
||||
__asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
#include <config.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
#define __secure __attribute__ ((section ("._secure.text")))
|
||||
#define __secure_data __attribute__ ((section ("._secure.data")))
|
||||
#define __secure __section("._secure.text")
|
||||
#define __secure_data __section("._secure.data")
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
@ -22,7 +22,7 @@ typedef struct secure_svc_tbl {
|
|||
*/
|
||||
#define DECLARE_SECURE_SVC(_name, _id, _fn) \
|
||||
static const secure_svc_tbl_t __secure_svc_ ## _name \
|
||||
__attribute__((used, section("._secure_svc_tbl_entries"))) \
|
||||
__used __section("._secure_svc_tbl_entries") \
|
||||
= { \
|
||||
.id = _id, \
|
||||
.func = _fn }
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ struct tagtable {
|
|||
int (*parse)(const struct tag *);
|
||||
};
|
||||
|
||||
#define __tag __attribute__((unused, __section__(".taglist")))
|
||||
#define __tag __attribute__((unused)) __section(".taglist")
|
||||
#define __tagtable(tag, fn) \
|
||||
static struct tagtable __tagtable_##fn __tag = { tag, fn }
|
||||
|
||||
|
|
|
|||
|
|
@ -45,6 +45,8 @@ obj-$(CONFIG_SEMIHOSTING) += semihosting.o
|
|||
|
||||
obj-y += bdinfo.o
|
||||
obj-y += sections.o
|
||||
CFLAGS_REMOVE_sections.o := $(LTO_CFLAGS)
|
||||
|
||||
obj-y += stack.o
|
||||
ifdef CONFIG_CPU_V7M
|
||||
obj-y += interrupts_m.o
|
||||
|
|
@ -64,6 +66,7 @@ endif
|
|||
|
||||
obj-y += cache.o
|
||||
obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
|
||||
CFLAGS_REMOVE_cache-cp15.o := $(LTO_CFLAGS)
|
||||
|
||||
obj-y += psci-dt.o
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
/*
|
||||
* Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
|
||||
/**
|
||||
* These two symbols are declared in a C file so that the linker
|
||||
|
|
@ -18,18 +19,18 @@
|
|||
* aliasing warnings.
|
||||
*/
|
||||
|
||||
char __bss_start[0] __attribute__((section(".__bss_start")));
|
||||
char __bss_end[0] __attribute__((section(".__bss_end")));
|
||||
char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
|
||||
char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
|
||||
char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
|
||||
char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
|
||||
char __secure_start[0] __attribute__((section(".__secure_start")));
|
||||
char __secure_end[0] __attribute__((section(".__secure_end")));
|
||||
char __secure_stack_start[0] __attribute__((section(".__secure_stack_start")));
|
||||
char __secure_stack_end[0] __attribute__((section(".__secure_stack_end")));
|
||||
char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
|
||||
char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
|
||||
char __efi_runtime_rel_start[0] __attribute__((section(".__efi_runtime_rel_start")));
|
||||
char __efi_runtime_rel_stop[0] __attribute__((section(".__efi_runtime_rel_stop")));
|
||||
char _end[0] __attribute__((section(".__end")));
|
||||
char __bss_start[0] __section(".__bss_start");
|
||||
char __bss_end[0] __section(".__bss_end");
|
||||
char __image_copy_start[0] __section(".__image_copy_start");
|
||||
char __image_copy_end[0] __section(".__image_copy_end");
|
||||
char __rel_dyn_start[0] __section(".__rel_dyn_start");
|
||||
char __rel_dyn_end[0] __section(".__rel_dyn_end");
|
||||
char __secure_start[0] __section(".__secure_start");
|
||||
char __secure_end[0] __section(".__secure_end");
|
||||
char __secure_stack_start[0] __section(".__secure_stack_start");
|
||||
char __secure_stack_end[0] __section(".__secure_stack_end");
|
||||
char __efi_runtime_start[0] __section(".__efi_runtime_start");
|
||||
char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
|
||||
char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start");
|
||||
char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop");
|
||||
char _end[0] __section(".__end");
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
* WARNING: This is going away very soon. Don't use it and don't submit
|
||||
* pafches that rely on it. The global_data area is set up in crt0.S.
|
||||
*/
|
||||
gd_t gdata __attribute__ ((section(".data")));
|
||||
gd_t gdata __section(".data");
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ void at91_disable_wdt(void)
|
|||
#include <asm/arch/sama5_boot.h>
|
||||
struct {
|
||||
u32 r4;
|
||||
} bootrom_stash __attribute__((section(".data")));
|
||||
} bootrom_stash __section(".data");
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ void memzero(void *s, size_t n)
|
|||
*/
|
||||
static void setup_global_data(gd_t *gdp)
|
||||
{
|
||||
gd = gdp;
|
||||
set_gd(gdp);
|
||||
memzero((void *)gd, sizeof(gd_t));
|
||||
gd->flags |= GD_FLG_RELOC;
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@ choice
|
|||
prompt "NXP i.MX8M board select"
|
||||
optional
|
||||
|
||||
config TARGET_IMX8MQ_CM
|
||||
bool "Ronetix iMX8MQ-CM SoM"
|
||||
select BINMAN
|
||||
select IMX8MQ
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MQ_EVK
|
||||
bool "imx8mq_evk"
|
||||
select IMX8MQ
|
||||
|
|
@ -45,6 +51,24 @@ config TARGET_IMX8MM_EVK
|
|||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MM_ICORE_MX8MM
|
||||
bool "Engicam i.Core MX8M Mini SOM"
|
||||
select IMX8MM
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
help
|
||||
i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM.
|
||||
|
||||
i.Core MX8M Mini EDIMM2.2:
|
||||
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
|
||||
* i.Core MX8M Mini needs to mount on top of EDIMM2.2 for
|
||||
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
|
||||
|
||||
i.Core MX8M Mini C.TOUCH 2.0
|
||||
* C.TOUCH 2.0 is a general purpose Carrier board.
|
||||
* i.Core MX8M Mini needs to mount on top of this Carrier board
|
||||
for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
|
||||
|
||||
config TARGET_IMX8MM_VENICE
|
||||
bool "Support Gateworks Venice iMX8M Mini module"
|
||||
select IMX8MM
|
||||
|
|
@ -106,19 +130,29 @@ config TARGET_PHYCORE_IMX8MP
|
|||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MM_CL_IOT_GATE
|
||||
bool "CompuLab iot-gate-imx8"
|
||||
select BINMAN
|
||||
select IMX8MM
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
endchoice
|
||||
|
||||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mn/Kconfig"
|
||||
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
|
||||
source "board/engicam/imx8mm/Kconfig"
|
||||
source "board/freescale/imx8mq_evk/Kconfig"
|
||||
source "board/freescale/imx8mm_evk/Kconfig"
|
||||
source "board/freescale/imx8mn_evk/Kconfig"
|
||||
source "board/freescale/imx8mp_evk/Kconfig"
|
||||
source "board/gateworks/venice/Kconfig"
|
||||
source "board/google/imx8mq_phanbell/Kconfig"
|
||||
source "board/technexion/pico-imx8mq/Kconfig"
|
||||
source "board/toradex/verdin-imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mn/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
source "board/ronetix/imx8mq-cm/Kconfig"
|
||||
source "board/technexion/pico-imx8mq/Kconfig"
|
||||
source "board/toradex/verdin-imx8mm/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -846,7 +846,7 @@ int set_clk_eqos(enum enet_freq type)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int imx_eqos_txclk_set_rate(u32 rate)
|
||||
int imx_eqos_txclk_set_rate(ulong rate)
|
||||
{
|
||||
u32 val;
|
||||
u32 eqos_post_div;
|
||||
|
|
|
|||
|
|
@ -537,7 +537,7 @@ enum boot_device get_boot_device(void)
|
|||
|
||||
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
|
||||
((uintptr_t)&boot) ^ QUERY_BT_DEV);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
puts("ROMAPI: failure at query_boot_info\n");
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ if [ ! -f $BL31 ]; then
|
|||
exit 0
|
||||
else
|
||||
echo "$BL31 size: " >&2
|
||||
ls -lct $BL31 | awk '{print $5}' >&2
|
||||
stat -c %s $BL31 >&2
|
||||
fi
|
||||
|
||||
BL32="tee.bin"
|
||||
|
|
@ -26,7 +26,7 @@ if [ ! -f $BL32 ]; then
|
|||
else
|
||||
echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
|
||||
echo "$BL32 size: " >&2
|
||||
ls -lct $BL32 | awk '{print $5}' >&2
|
||||
stat -c %s $BL32 >&2
|
||||
fi
|
||||
|
||||
BL33="u-boot-nodtb.bin"
|
||||
|
|
@ -36,13 +36,13 @@ if [ ! -f $BL33 ]; then
|
|||
exit 0
|
||||
else
|
||||
echo "u-boot-nodtb.bin size: " >&2
|
||||
ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
|
||||
stat -c %s u-boot-nodtb.bin >&2
|
||||
fi
|
||||
|
||||
for dtname in $*
|
||||
do
|
||||
echo "$dtname size: " >&2
|
||||
ls -lct $dtname | awk '{print $5}' >&2
|
||||
stat -c %s $dtname >&2
|
||||
done
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -35,6 +35,15 @@ config TARGET_CL_SOM_IMX7
|
|||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_IMX7_CM
|
||||
bool "Ronetix iMX7-CM"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select MX7D
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_MEERKAT96
|
||||
bool "NovTech Meerkat96 board"
|
||||
select BOARD_LATE_INIT
|
||||
|
|
@ -82,6 +91,7 @@ config SYS_SOC
|
|||
default "mx7"
|
||||
|
||||
source "board/compulab/cl-som-imx7/Kconfig"
|
||||
source "board/ronetix/imx7-cm/Kconfig"
|
||||
source "board/freescale/mx7dsabresd/Kconfig"
|
||||
source "board/novtech/meerkat96/Kconfig"
|
||||
source "board/technexion/pico-imx7d/Kconfig"
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ static ulong spl_romapi_read_seekable(struct spl_load_info *load,
|
|||
|
||||
ret = g_rom_api->download_image(buf, offset, byte,
|
||||
((uintptr_t)buf) ^ offset ^ byte);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret == ROM_API_OKAY)
|
||||
return count;
|
||||
|
|
@ -73,7 +73,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
|
|||
ret |= g_rom_api->query_boot_infor(QUERY_IMG_OFF, &image_offset,
|
||||
((uintptr_t)&image_offset) ^ QUERY_IMG_OFF);
|
||||
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
puts("ROMAPI: Failure query boot infor pagesize/offset\n");
|
||||
|
|
@ -94,7 +94,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
|
|||
size = ALIGN(sizeof(struct image_header), pagesize);
|
||||
ret = g_rom_api->download_image((u8 *)header, offset, size,
|
||||
((uintptr_t)header) ^ offset ^ size);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
printf("ROMAPI: download failure offset 0x%x size 0x%x\n",
|
||||
|
|
@ -180,7 +180,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
|
|||
|
||||
ret = g_rom_api->query_boot_infor(QUERY_PAGE_SZ, &pagesize,
|
||||
((uintptr_t)&pagesize) ^ QUERY_PAGE_SZ);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY)
|
||||
puts("failure at query_boot_info\n");
|
||||
|
|
@ -192,7 +192,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
|
|||
for (i = 0; i < 640; i++) {
|
||||
ret = g_rom_api->download_image(p, 0, pg,
|
||||
((uintptr_t)p) ^ pg);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
puts("Steam(USB) download failure\n");
|
||||
|
|
@ -213,7 +213,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
|
|||
|
||||
if (p - pfit < sizeof(struct fdt_header)) {
|
||||
ret = g_rom_api->download_image(p, 0, pg, ((uintptr_t)p) ^ pg);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
puts("Steam(USB) download failure\n");
|
||||
|
|
@ -237,7 +237,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
|
|||
|
||||
ret = g_rom_api->download_image(p, 0, imagesize,
|
||||
((uintptr_t)p) ^ imagesize);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
p += imagesize;
|
||||
|
||||
|
|
@ -280,7 +280,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
|
|||
|
||||
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
|
||||
((uintptr_t)&boot) ^ QUERY_BT_DEV);
|
||||
gd = pgd;
|
||||
set_gd(pgd);
|
||||
|
||||
if (ret != ROM_API_OKAY) {
|
||||
puts("ROMAPI: failure at query_boot_info\n");
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue