mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
f29eaadeb5
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
218 lines
4.6 KiB
Plaintext
218 lines
4.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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#undef CP110_NAME
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#undef CP110_NUM
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#undef CP110_PCIE_MEM_SIZE
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#undef CP110_PCIEx_CPU_MEM_BASE
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#undef CP110_PCIEx_BUS_MEM_BASE
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/* CP110-2 Settings */
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#define CP110_NAME cp2
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#define CP110_NUM 2
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#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
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#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
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#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
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#include "armada-cp110.dtsi"
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/ {
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model = "Marvell CN9132 development board";
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compatible = "marvell,cn9132-db";
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aliases {
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gpio5 = &cp2_gpio0;
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gpio6 = &cp2_gpio1;
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};
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cp2 {
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config-space {
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sdhci@780000 {
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vqmmc-supply = <&cp2_reg_sd_vccq>;
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};
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cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <100000>;
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regulator-force-boot-off;
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gpio = <&cp2_gpio0 2 GPIO_ACTIVE_HIGH>;
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};
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cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <100000>;
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regulator-force-boot-off;
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gpio = <&cp2_gpio0 3 GPIO_ACTIVE_HIGH>;
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};
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cp2_reg_sd_vccq: cp2_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp2_sd_vcc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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/* cp2_mpp49 */
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gpios = <&cp2_gpio1 17 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp2_reg_usb3_current_lim0: cp2_usb3_current_limiter@0 {
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compatible = "regulator-fixed";
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regulator-min-microamp = <900000>;
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regulator-max-microamp = <900000>;
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regulator-force-boot-off;
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gpio = <&cp2_gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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cp2_reg_usb3_current_lim1: cp2_usb3_current_limiter@1 {
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compatible = "regulator-fixed";
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regulator-min-microamp = <900000>;
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regulator-max-microamp = <900000>;
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regulator-force-boot-off;
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gpio = <&cp2_gpio0 1 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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};
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&cp2_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp2_pinctl {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,cp115-standalone-pinctrl";
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bank-name ="cp2-110";
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/* MPP Bus:
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* [0-26] GPIO
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* [27] SATA0_PRESENT_ACTIVEn
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* [28] SATA1_PRESENT_ACTIVEn
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* [29-31, 33] GPIO (Default)
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* [32,34] SMI
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* [37-38] I2C0
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* [39-53] GPIO
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* [54] SD_CRD_RSTn (out)
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* [55] SD_CRD_DT (in)
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* [56-62] SDIO
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x0
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0x0 0x0 0x8 0x0 0x8 0x0 0x0 0x2 0x2 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0xa 0xb 0xe 0xe 0xe 0xe
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0xe 0xe 0xe >;
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cp2_i2c0_pins: cp2-i2c-pins-0 {
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marvell,pins = < 37 38 >;
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marvell,function = <2>;
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};
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cp2_sdhci_pins: cp2-sdhi-pins-0 {
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marvell,pins = < 56 57 58 59 60 61 >;
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marvell,function = <14>;
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};
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};
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&cp2_usb3_0 {
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status = "okay";
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vbus-supply = <&cp2_reg_usb3_vbus0>;
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current-limiter = <&cp2_reg_usb3_current_lim0>;
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vbus-disable-delay = <500>;
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};
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/* SLM-1521-V2, CON11 */
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&cp2_usb3_1 {
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status = "okay";
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vbus-supply = <&cp2_reg_usb3_vbus1>;
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current-limiter = <&cp2_reg_usb3_current_lim1>;
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vbus-disable-delay = <500>;
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status = "okay";
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};
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&cp2_utmi0 {
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status = "okay";
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};
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&cp2_utmi1 {
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status = "okay";
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};
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&cp2_comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_PEX2>;
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};
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};
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&cp2_ethernet {
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status = "okay";
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};
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/* SLM-1521-V2, CON9 */
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&cp2_eth0 {
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status = "okay";
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phy-mode = "sfi";
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};
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/* SLM-1521-V2, CON6 */
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&cp2_pcie0 {
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/* non-prefetchable memory */
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ranges =<0x82000000 0 0xe5000000 0 0xe5000000 0 0x1000000>;
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num-lanes = <2>;
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status = "okay";
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};
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/* SLM-1521-V2, CON8 */
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&cp2_pcie2 {
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num-lanes = <1>;
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status = "okay";
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};
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&cp2_pinctl {
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};
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/* SLM-1521-V2, CON4 */
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&cp2_sata0 {
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status = "okay";
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};
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/* CON 2 on SLM-1683 - microSD */
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&cp2_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_sdhci_pins>;
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bus-width = <4>;
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status = "okay";
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};
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