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https://github.com/brain-hackers/u-boot-brain
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f29eaadeb5
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
52 lines
1011 B
Plaintext
52 lines
1011 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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#include "cn9130-db.dtsi"
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/ {
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model = "Marvell CN9130 development board (CP NAND) setup(B)";
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};
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/*
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* CP related configuration
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*/
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&cp0_pinctl {
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/* MPP Bus:
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* [0-11] RGMII1
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* [12] GPIO GE-IN
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* [13-14] SPI1
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* [15-27] NAND
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* [28] MSS_GPIO[5] XXX:(mode nr from a3900)
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* [29-30] SATA
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* [31] MSS_GPIO[4] XXX:(mode nr from a3900)
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* [32,34] SMI
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* [33] SDIO
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* [35-36] I2C1
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* [37-38] I2C0
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* [39-43] SDIOctrl
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* [44-55] RGMII2
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* [56-62] SDIO
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 3 3 3 3 3 3 3 3 3 3
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3 3 0 2 3 1 1 1 1 1
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1 1 1 1 1 1 1 1 3 9
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9 3 7 6 7 2 2 2 2 1
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1 1 1 1 1 1 1 1 1 1
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1 1 1 1 1 1 0xe 0xe 0xe 0xe
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0xe 0xe 0xe>;
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};
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/* U54 */
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&cp0_nand {
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status = "okay";
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};
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/* U55 */
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&cp0_spi1 {
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status = "disabled";
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};
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