mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Daniel Schwierzeck
parent
59aea37abf
commit
0dc4ab9c43
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@ -770,6 +770,12 @@ M: Ezequiel Garcia <ezequiel@collabora.com>
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S: Maintained
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F: arch/mips/mach-jz47xx/
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MIPS Octeon
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M: Aaron Williams <awilliams@marvell.com>
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S: Maintained
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F: arch/mips/mach-octeon/
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F: arch/mips/include/asm/arch-octeon/
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MMC
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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@ -106,6 +106,25 @@ config ARCH_JZ47XX
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select OF_CONTROL
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select DM
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config ARCH_OCTEON
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bool "Support Marvell Octeon CN7xxx platforms"
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select CPU_CAVIUM_OCTEON
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select DISPLAY_CPUINFO
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select DMA_ADDR_T_64BIT
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select DM
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select DM_SERIAL
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select DM_GPIO
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select DM_ETH
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select MIPS_L2_CACHE
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select MIPS_TUNE_OCTEON3
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS64_OCTEON
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select PHYS_64BIT
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select OF_CONTROL
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select OF_LIVE
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imply CMD_DM
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config MACH_PIC32
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bool "Support Microchip PIC32"
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select DM
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@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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source "arch/mips/mach-octeon/Kconfig"
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if MIPS
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@ -233,6 +253,14 @@ config CPU_MIPS64_R6
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Choose this option to build a kernel for release 6 or later of the
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MIPS64 architecture.
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config CPU_MIPS64_OCTEON
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bool "Marvell Octeon series of CPUs"
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depends on SUPPORTS_CPU_MIPS64_OCTEON
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select 64BIT
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help
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Choose this option for Marvell Octeon CPUs. These CPUs are between
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MIPS64 R5 and R6 with other extensions.
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endchoice
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menu "General setup"
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@ -431,6 +459,12 @@ config SUPPORTS_CPU_MIPS64_R2
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config SUPPORTS_CPU_MIPS64_R6
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bool
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config SUPPORTS_CPU_MIPS64_OCTEON
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bool
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config CPU_CAVIUM_OCTEON
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bool
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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@ -438,6 +472,7 @@ config CPU_MIPS32
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config CPU_MIPS64
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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default y if CPU_MIPS64_OCTEON
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config MIPS_TUNE_4KC
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bool
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@ -454,6 +489,9 @@ config MIPS_TUNE_34KC
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config MIPS_TUNE_74KC
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bool
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config MIPS_TUNE_OCTEON3
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bool
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config 32BIT
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bool
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@ -486,6 +524,11 @@ config MIPS_SRAM_INIT
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before it can be used. If enabled, a function mips_sram_init() will
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be called just before setup_stack_gd.
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config DMA_ADDR_T_64BIT
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bool
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help
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Select this to enable 64-bit DMA addressing
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config SYS_DCACHE_SIZE
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int
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default 0
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@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
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machine-$(CONFIG_MACH_PIC32) += pic32
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machine-$(CONFIG_ARCH_MTMIPS) += mtmips
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machine-$(CONFIG_ARCH_MSCC) += mscc
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machine-${CONFIG_ARCH_OCTEON} += octeon
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machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
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libs-y += $(machdirs)
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@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
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arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
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arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
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arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
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arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
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# Allow extra optimization for specific CPUs/SoCs
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tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
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@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
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tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
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tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
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tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
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tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
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# Include default header files
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cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
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@ -0,0 +1,46 @@
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menu "Octeon platforms"
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depends on ARCH_OCTEON
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config SYS_SOC
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string
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default "octeon"
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config OCTEON_CN7XXX
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bool "Octeon CN7XXX SoC"
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config OCTEON_CN70XX
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bool "Octeon CN70XX SoC"
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select OCTEON_CN7XXX
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config OCTEON_CN73XX
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bool "Octeon CN73XX SoC"
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select OCTEON_CN7XXX
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config OCTEON_CN78XX
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bool "Octeon CN78XX SoC"
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select OCTEON_CN7XXX
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choice
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prompt "Octeon MIPS family select"
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config SOC_OCTEON3
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bool "Octeon III family"
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help
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This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
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and CNF75XX.
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endchoice
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 128
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config SYS_ICACHE_SIZE
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default 79872
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config SYS_ICACHE_LINE_SIZE
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default 128
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endmenu
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@ -0,0 +1,10 @@
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# (C) Copyright 2019 Marvell, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += lowlevel_init.o
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obj-y += cache.o
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obj-y += clock.o
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obj-y += cpu.o
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obj-y += dram.o
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@ -0,0 +1,24 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <cpu_func.h>
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/*
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* The Octeon platform is cache coherent and cache flushes and invalidates
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* are not needed. Define some platform specific empty flush_foo()
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* functions here to overwrite the _weak common function as a no-op.
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* This effectively disables all cache operations.
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*/
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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}
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@ -0,0 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018, 2019 Marvell International Ltd.
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*/
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#include <asm/global_data.h>
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#include <mach/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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ulong notrace get_tbclk(void)
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{
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return gd->cpu_clk;
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}
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@ -0,0 +1,66 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <asm/global_data.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/io.h>
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#include <mach/clock.h>
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#include <mach/cavm-reg.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int get_clocks(void)
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{
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const u64 ref_clock = PLL_REF_CLK;
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void __iomem *rst_boot;
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u64 val;
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rst_boot = ioremap(CAVM_RST_BOOT, 0);
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val = ioread64(rst_boot);
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gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
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gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
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debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
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return 0;
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}
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/* Early mach init code run from flash */
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int mach_cpu_init(void)
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{
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void __iomem *mio_boot_reg_cfg0;
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/* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
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/* ToDo: Move this to an early running bus (bootbus) DM driver */
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mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
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clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
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/* Get clocks and store them in GD */
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get_clocks();
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return 0;
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}
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/**
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* Returns number of cores
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*
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* @return number of CPU cores for the specified node
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*/
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static int cavm_octeon_num_cores(void)
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{
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void __iomem *ciu_fuse;
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ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
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return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
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}
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int print_cpuinfo(void)
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{
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printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
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return 0;
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}
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) Stefan Roese <sr@denx.de>
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*/
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#include <dm.h>
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#include <ram.h>
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#include <asm/global_data.h>
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#include <linux/compat.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/*
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* No DDR init yet -> run in L2 cache
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*/
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gd->ram_size = (4 << 20);
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gd->bd->bi_dram[0].size = gd->ram_size;
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gd->bd->bi_dram[1].size = 0;
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return 0;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return gd->ram_top;
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}
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_MACH_OCTEON_IOREMAP_H
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#define __ASM_MACH_OCTEON_IOREMAP_H
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#include <linux/types.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
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phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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return (void __iomem *)(XKPHYS | offset);
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return 0;
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}
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#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
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#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CAVM_REG_H__
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/* Register offsets */
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#define CAVM_CIU_FUSE 0x00010100000001a0
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#define CAVM_MIO_BOOT_REG_CFG0 0x0001180000000000
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#define CAVM_RST_BOOT 0x0001180006001600
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/* Register bits */
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#define RST_BOOT_C_MUL GENMASK_ULL(36, 30)
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#define RST_BOOT_PNR_MUL GENMASK_ULL(29, 24)
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#endif /* __CAVM_REG_H__ */
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018, 2019 Marvell International Ltd.
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*/
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#ifndef __CLOCK_H__
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/** System PLL reference clock */
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#define PLL_REF_CLK 50000000 /* 50 MHz */
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#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
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#endif /* __CLOCK_H__ */
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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.set noreorder
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LEAF(lowlevel_init)
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jr ra
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nop
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END(lowlevel_init)
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@ -228,7 +228,6 @@ CONFIG_CPLD_BR_PRELIM
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CONFIG_CPLD_OR_PRELIM
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CONFIG_CPM2
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CONFIG_CPU_ARMV8
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CONFIG_CPU_CAVIUM_OCTEON
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CONFIG_CPU_FREQ_HZ
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CONFIG_CPU_HAS_LLSC
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CONFIG_CPU_HAS_PREFETCH
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