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https://github.com/brain-hackers/u-boot-brain
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0dc4ab9c43
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
25 lines
560 B
C
25 lines
560 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <cpu_func.h>
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/*
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* The Octeon platform is cache coherent and cache flushes and invalidates
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* are not needed. Define some platform specific empty flush_foo()
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* functions here to overwrite the _weak common function as a no-op.
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* This effectively disables all cache operations.
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*/
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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}
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