mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
0dc4ab9c43
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
18 lines
424 B
C
18 lines
424 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CAVM_REG_H__
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/* Register offsets */
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#define CAVM_CIU_FUSE 0x00010100000001a0
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#define CAVM_MIO_BOOT_REG_CFG0 0x0001180000000000
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#define CAVM_RST_BOOT 0x0001180006001600
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/* Register bits */
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#define RST_BOOT_C_MUL GENMASK_ULL(36, 30)
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#define RST_BOOT_PNR_MUL GENMASK_ULL(29, 24)
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#endif /* __CAVM_REG_H__ */
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