2018-05-07 06:58:06 +09:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2012-09-28 18:56:37 +09:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
|
2018-01-17 15:37:47 +09:00
|
|
|
* (C) Copyright 2013 - 2018 Xilinx, Inc.
|
2012-09-28 18:56:37 +09:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2019-11-15 04:57:46 +09:00
|
|
|
#include <init.h>
|
2018-02-22 01:04:28 +09:00
|
|
|
#include <dm/uclass.h>
|
2019-08-02 00:46:51 +09:00
|
|
|
#include <env.h>
|
2014-02-24 19:16:32 +09:00
|
|
|
#include <fdtdec.h>
|
2014-04-25 20:51:17 +09:00
|
|
|
#include <fpga.h>
|
2019-01-25 20:36:06 +09:00
|
|
|
#include <malloc.h>
|
2014-04-25 20:51:17 +09:00
|
|
|
#include <mmc.h>
|
2018-06-08 20:45:14 +09:00
|
|
|
#include <watchdog.h>
|
2018-02-22 01:04:28 +09:00
|
|
|
#include <wdt.h>
|
2013-04-22 22:43:02 +09:00
|
|
|
#include <zynqpl.h>
|
2013-04-12 23:33:08 +09:00
|
|
|
#include <asm/arch/hardware.h>
|
|
|
|
#include <asm/arch/sys_proto.h>
|
2012-09-28 18:56:37 +09:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
|
|
|
int board_init(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-09 05:18:21 +09:00
|
|
|
int board_late_init(void)
|
|
|
|
{
|
2019-01-25 20:36:06 +09:00
|
|
|
int env_targets_len = 0;
|
|
|
|
const char *mode;
|
|
|
|
char *new_targets;
|
|
|
|
char *env_targets;
|
|
|
|
|
2014-01-09 05:18:21 +09:00
|
|
|
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
|
2016-12-16 21:16:14 +09:00
|
|
|
case ZYNQ_BM_QSPI:
|
2019-01-25 20:36:06 +09:00
|
|
|
mode = "qspi";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "qspiboot");
|
2016-12-16 21:16:14 +09:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_NAND:
|
2019-01-25 20:36:06 +09:00
|
|
|
mode = "nand";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "nandboot");
|
2016-12-16 21:16:14 +09:00
|
|
|
break;
|
2014-01-09 05:18:21 +09:00
|
|
|
case ZYNQ_BM_NOR:
|
2019-01-25 20:36:06 +09:00
|
|
|
mode = "nor";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "norboot");
|
2014-01-09 05:18:21 +09:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_SD:
|
2019-09-11 19:51:49 +09:00
|
|
|
mode = "mmc0";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "sdboot");
|
2014-01-09 05:18:21 +09:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_JTAG:
|
2019-01-25 20:36:06 +09:00
|
|
|
mode = "pxe dhcp";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "jtagboot");
|
2014-01-09 05:18:21 +09:00
|
|
|
break;
|
|
|
|
default:
|
2019-01-25 20:36:06 +09:00
|
|
|
mode = "";
|
2017-08-04 03:22:09 +09:00
|
|
|
env_set("modeboot", "");
|
2014-01-09 05:18:21 +09:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-01-25 20:36:06 +09:00
|
|
|
/*
|
|
|
|
* One terminating char + one byte for space between mode
|
|
|
|
* and default boot_targets
|
|
|
|
*/
|
|
|
|
env_targets = env_get("boot_targets");
|
|
|
|
if (env_targets)
|
|
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
|
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
|
|
|
|
if (!new_targets)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
sprintf(new_targets, "%s %s", mode,
|
|
|
|
env_targets ? env_targets : "");
|
|
|
|
|
|
|
|
env_set("boot_targets", new_targets);
|
|
|
|
|
2019-12-18 19:34:41 +09:00
|
|
|
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
|
|
|
|
|
2014-01-09 05:18:21 +09:00
|
|
|
return 0;
|
|
|
|
}
|
2012-09-28 18:56:37 +09:00
|
|
|
|
2016-04-01 22:56:33 +09:00
|
|
|
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
|
2017-03-31 23:40:32 +09:00
|
|
|
int dram_init_banksize(void)
|
2016-12-09 21:56:54 +09:00
|
|
|
{
|
2017-11-03 23:25:51 +09:00
|
|
|
return fdtdec_setup_memory_banksize();
|
2016-12-09 21:56:54 +09:00
|
|
|
}
|
2016-12-07 00:31:53 +09:00
|
|
|
|
2016-12-09 21:56:54 +09:00
|
|
|
int dram_init(void)
|
|
|
|
{
|
2018-07-16 19:26:11 +09:00
|
|
|
if (fdtdec_setup_mem_size_base() != 0)
|
2016-12-18 23:03:34 +09:00
|
|
|
return -EINVAL;
|
2016-12-04 18:33:22 +09:00
|
|
|
|
2016-12-09 21:56:54 +09:00
|
|
|
zynq_ddrc_init();
|
2016-12-04 18:33:22 +09:00
|
|
|
|
2016-12-09 21:56:54 +09:00
|
|
|
return 0;
|
2016-04-01 22:56:33 +09:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
int dram_init(void)
|
|
|
|
{
|
2018-04-11 23:12:28 +09:00
|
|
|
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
|
|
|
CONFIG_SYS_SDRAM_SIZE);
|
2016-04-01 22:56:33 +09:00
|
|
|
|
2013-06-17 21:37:01 +09:00
|
|
|
zynq_ddrc_init();
|
|
|
|
|
2012-09-28 18:56:37 +09:00
|
|
|
return 0;
|
|
|
|
}
|
2016-04-01 22:56:33 +09:00
|
|
|
#endif
|