2012-09-28 18:56:37 +09:00
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/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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*
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2013-10-07 20:07:26 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-09-28 18:56:37 +09:00
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*/
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#include <common.h>
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2014-02-24 19:16:32 +09:00
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#include <fdtdec.h>
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2014-04-25 20:51:17 +09:00
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#include <fpga.h>
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#include <mmc.h>
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2013-04-22 22:43:02 +09:00
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#include <zynqpl.h>
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2013-04-12 23:33:08 +09:00
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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2012-09-28 18:56:37 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga;
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2013-04-22 22:43:02 +09:00
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/* It can be done differently */
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2016-10-18 23:10:25 +09:00
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static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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2016-10-18 23:10:25 +09:00
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static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
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static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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2014-11-25 18:59:54 +09:00
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static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
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static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
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2013-04-22 22:43:02 +09:00
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#endif
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2012-09-28 18:56:37 +09:00
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int board_init(void)
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{
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2013-04-22 22:43:02 +09:00
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u32 idcode;
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idcode = zynq_slcr_get_idcode();
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switch (idcode) {
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2016-10-18 23:10:25 +09:00
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case XILINX_ZYNQ_7007S:
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fpga = fpga007s;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7010:
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fpga = fpga010;
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break;
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2016-10-18 23:10:25 +09:00
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case XILINX_ZYNQ_7012S:
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fpga = fpga012s;
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break;
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case XILINX_ZYNQ_7014S:
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fpga = fpga014s;
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break;
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2013-09-26 23:39:03 +09:00
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case XILINX_ZYNQ_7015:
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fpga = fpga015;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7020:
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fpga = fpga020;
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break;
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case XILINX_ZYNQ_7030:
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fpga = fpga030;
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break;
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2014-11-25 18:59:54 +09:00
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case XILINX_ZYNQ_7035:
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fpga = fpga035;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7045:
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fpga = fpga045;
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break;
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2013-06-17 20:54:07 +09:00
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case XILINX_ZYNQ_7100:
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fpga = fpga100;
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break;
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2013-04-22 22:43:02 +09:00
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}
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#endif
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2013-04-22 22:43:02 +09:00
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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#endif
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2012-09-28 18:56:37 +09:00
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return 0;
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}
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2014-01-09 05:18:21 +09:00
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int board_late_init(void)
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{
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_NOR:
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setenv("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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setenv("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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setenv("modeboot", "jtagboot");
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break;
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default:
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setenv("modeboot", "");
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break;
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}
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return 0;
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}
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2012-09-28 18:56:37 +09:00
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2014-08-28 20:31:02 +09:00
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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2016-01-25 19:04:21 +09:00
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puts("Board: Xilinx Zynq\n");
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2014-08-28 20:31:02 +09:00
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return 0;
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}
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#endif
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2016-01-27 02:57:03 +09:00
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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2016-04-01 22:56:33 +09:00
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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2016-12-09 21:56:54 +09:00
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/*
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* fdt_get_reg - Fill buffer by information from DT
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*/
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static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
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const u32 *cell, int n)
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2016-04-01 22:56:33 +09:00
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{
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2016-12-09 21:56:54 +09:00
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int i = 0, b, banks;
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int parent_offset = fdt_parent_offset(fdt, nodeoffset);
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int address_cells = fdt_address_cells(fdt, parent_offset);
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int size_cells = fdt_size_cells(fdt, parent_offset);
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char *p = buf;
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u64 val;
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u64 vals;
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debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
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__func__, address_cells, size_cells, buf, cell);
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/* Check memory bank setup */
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banks = n % (address_cells + size_cells);
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if (banks)
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panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
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n, address_cells, size_cells);
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banks = n / (address_cells + size_cells);
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for (b = 0; b < banks; b++) {
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debug("%s: Bank #%d:\n", __func__, b);
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if (address_cells == 2) {
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val = cell[i + 1];
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val <<= 32;
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val |= cell[i];
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val = fdt64_to_cpu(val);
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debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
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__func__, val, p, &cell[i]);
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*(phys_addr_t *)p = val;
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} else {
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debug("%s: addr32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_addr_t);
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i += address_cells;
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debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
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sizeof(phys_addr_t));
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if (size_cells == 2) {
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vals = cell[i + 1];
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vals <<= 32;
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vals |= cell[i];
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vals = fdt64_to_cpu(vals);
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debug("%s: size64=%llx, ptr=%p, cell=%p\n",
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__func__, vals, p, &cell[i]);
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*(phys_size_t *)p = vals;
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} else {
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debug("%s: size32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_size_t);
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i += size_cells;
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debug("%s: ps=%p, i=%x, size=%zu\n",
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__func__, p, i, sizeof(phys_size_t));
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}
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2016-04-01 22:56:33 +09:00
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2016-12-09 21:56:54 +09:00
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/* Return the first address size */
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return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
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2016-12-04 18:33:22 +09:00
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}
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2016-04-01 22:56:33 +09:00
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2016-12-09 21:56:54 +09:00
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#define FDT_REG_SIZE sizeof(u32)
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/* Temp location for sharing data for storing */
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/* Up to 64-bit address + 64-bit size */
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static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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void dram_init_banksize(void)
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{
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int bank;
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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debug("Bank #%d: start %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].start);
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debug("Bank #%d: size %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].size);
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}
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}
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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int dram_init(void)
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{
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int node, len;
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const void *blob = gd->fdt_blob;
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const u32 *cell;
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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memset(&tmp, 0, sizeof(tmp));
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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/* find or create "/memory" node. */
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node = fdt_subnode_offset(blob, 0, "memory");
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if (node < 0) {
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printf("%s: Can't get memory node\n", __func__);
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return node;
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}
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2016-12-07 00:31:53 +09:00
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2016-12-09 21:56:54 +09:00
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/* Get pointer to cells and lenght of it */
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell) {
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printf("%s: Can't get reg property\n", __func__);
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return -1;
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2016-12-04 18:33:22 +09:00
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}
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2016-04-01 22:56:33 +09:00
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2016-12-09 21:56:54 +09:00
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gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
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2016-04-01 22:56:33 +09:00
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2016-12-09 21:56:54 +09:00
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debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
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2016-12-04 18:33:22 +09:00
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2016-12-09 21:56:54 +09:00
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zynq_ddrc_init();
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2016-12-04 18:33:22 +09:00
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2016-12-09 21:56:54 +09:00
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return 0;
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2016-04-01 22:56:33 +09:00
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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2013-06-17 21:37:01 +09:00
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zynq_ddrc_init();
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2012-09-28 18:56:37 +09:00
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return 0;
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}
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2016-04-01 22:56:33 +09:00
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#endif
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