2012-09-28 18:56:37 +09:00
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/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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*
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2013-10-07 20:07:26 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-09-28 18:56:37 +09:00
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*/
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#include <common.h>
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2014-02-24 19:16:32 +09:00
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#include <fdtdec.h>
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2014-04-25 20:51:17 +09:00
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#include <fpga.h>
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#include <mmc.h>
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2013-04-22 22:43:02 +09:00
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#include <zynqpl.h>
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2013-04-12 23:33:08 +09:00
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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2012-09-28 18:56:37 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga;
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2013-04-22 22:43:02 +09:00
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/* It can be done differently */
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2016-10-18 23:10:25 +09:00
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static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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2016-10-18 23:10:25 +09:00
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static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
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static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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2014-11-25 18:59:54 +09:00
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static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
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2014-04-25 20:51:17 +09:00
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static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
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static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
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2013-04-22 22:43:02 +09:00
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#endif
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2012-09-28 18:56:37 +09:00
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int board_init(void)
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{
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2013-04-22 22:43:02 +09:00
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u32 idcode;
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idcode = zynq_slcr_get_idcode();
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switch (idcode) {
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2016-10-18 23:10:25 +09:00
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case XILINX_ZYNQ_7007S:
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fpga = fpga007s;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7010:
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fpga = fpga010;
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break;
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2016-10-18 23:10:25 +09:00
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case XILINX_ZYNQ_7012S:
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fpga = fpga012s;
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break;
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case XILINX_ZYNQ_7014S:
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fpga = fpga014s;
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break;
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2013-09-26 23:39:03 +09:00
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case XILINX_ZYNQ_7015:
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fpga = fpga015;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7020:
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fpga = fpga020;
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break;
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case XILINX_ZYNQ_7030:
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fpga = fpga030;
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break;
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2014-11-25 18:59:54 +09:00
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case XILINX_ZYNQ_7035:
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fpga = fpga035;
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break;
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2013-04-22 22:43:02 +09:00
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case XILINX_ZYNQ_7045:
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fpga = fpga045;
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break;
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2013-06-17 20:54:07 +09:00
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case XILINX_ZYNQ_7100:
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fpga = fpga100;
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break;
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2013-04-22 22:43:02 +09:00
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}
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#endif
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2014-03-04 20:41:05 +09:00
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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2013-04-22 22:43:02 +09:00
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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#endif
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2012-09-28 18:56:37 +09:00
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return 0;
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}
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2014-01-09 05:18:21 +09:00
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int board_late_init(void)
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{
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_NOR:
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setenv("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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setenv("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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setenv("modeboot", "jtagboot");
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break;
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default:
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setenv("modeboot", "");
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break;
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}
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return 0;
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}
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2012-09-28 18:56:37 +09:00
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2014-08-28 20:31:02 +09:00
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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2016-01-25 19:04:21 +09:00
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puts("Board: Xilinx Zynq\n");
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2014-08-28 20:31:02 +09:00
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return 0;
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}
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#endif
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2016-01-27 02:57:03 +09:00
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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2016-04-01 22:56:33 +09:00
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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2016-12-04 18:33:22 +09:00
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static const void *get_memory_reg_prop(const void *fdt, int *lenp)
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2016-04-01 22:56:33 +09:00
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{
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2016-12-04 18:33:22 +09:00
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int offset;
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2016-04-01 22:56:33 +09:00
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2016-12-04 18:33:22 +09:00
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offset = fdt_path_offset(fdt, "/memory");
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if (offset < 0)
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return NULL;
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2016-04-01 22:56:33 +09:00
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2016-12-04 18:33:22 +09:00
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return fdt_getprop(fdt, offset, "reg", lenp);
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}
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2016-04-01 22:56:33 +09:00
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2016-12-07 00:31:53 +09:00
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int dram_init(void)
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{
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const void *fdt = gd->fdt_blob;
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const fdt32_t *val;
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int ac, sc, len;
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ac = fdt_address_cells(fdt, 0);
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sc = fdt_size_cells(fdt, 0);
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if (ac < 0 || sc < 1 || sc > 2) {
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printf("invalid address/size cells\n");
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return -EINVAL;
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}
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val = get_memory_reg_prop(fdt, &len);
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if (len / sizeof(*val) < ac + sc)
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return -EINVAL;
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val += ac;
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gd->ram_size = fdtdec_get_number(val, sc);
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debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
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zynq_ddrc_init();
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return 0;
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}
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2016-04-01 22:56:33 +09:00
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void dram_init_banksize(void)
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{
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2016-12-04 18:33:22 +09:00
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const void *fdt = gd->fdt_blob;
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const fdt32_t *val;
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int ac, sc, cells, len, i;
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val = get_memory_reg_prop(fdt, &len);
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if (len < 0)
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return;
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ac = fdt_address_cells(fdt, 0);
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sc = fdt_size_cells(fdt, 0);
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if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
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printf("invalid address/size cells\n");
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return;
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}
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2016-04-01 22:56:33 +09:00
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2016-12-04 18:33:22 +09:00
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cells = ac + sc;
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2016-04-01 22:56:33 +09:00
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2016-12-04 18:33:22 +09:00
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len /= sizeof(*val);
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for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
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i++, len -= cells) {
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gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
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val += ac;
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gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
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val += sc;
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debug("DRAM bank %d: start = %08lx, size = %08lx\n",
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i, (unsigned long)gd->bd->bi_dram[i].start,
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(unsigned long)gd->bd->bi_dram[i].size);
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2016-04-01 22:56:33 +09:00
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}
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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2013-06-17 21:37:01 +09:00
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zynq_ddrc_init();
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2012-09-28 18:56:37 +09:00
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return 0;
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}
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2016-04-01 22:56:33 +09:00
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#endif
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