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Merge tag 'v5.4.73' into 5.4-2.3.x-imx
This is the 5.4.73 stable release
Conflicts:
- arch/arm/boot/dts/imx6sl.dtsi:
Commit [a1767c9019] in NXP tree is now covered with commit [5c4c2f437c]
from upstream.
- drivers/gpu/drm/mxsfb/mxsfb_drv.c:
Resolve merge hunk for patch [ed8b90d303] from upstream
- drivers/media/i2c/ov5640.c:
Patch [aa4bb8b883] in NXP tree is now covered by patches [79ec0578c7]
and [b2f8546056] from upstream. Changes from NXP patch [99aa4c8c18] are
covered in upstream version as well.
- drivers/net/ethernet/freescale/fec_main.c:
Fix merge fuzz for patch [9e70485b40] from upstream.
- drivers/usb/cdns3/gadget.c:
Keep NXP version of the file, upstream version is not compatible.
- drivers/usb/dwc3/core.c:
- drivers/usb/dwc3/core.h:
Fix merge fuzz of patch [08045050c6] together wth NXP patch [b30e41dc1e]
- sound/soc/fsl/fsl_sai.c:
- sound/soc/fsl/fsl_sai.h:
Commit [2ea70e51eb72a] in NXP tree is now covered with commit [1ad7f52fe6]
from upstream.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Fine tune the PHY parameters, let the PCIe link up to GEN3 between two
i.MX865 EVK boards in the i.MX EP RC validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 17db82300f80061a8568edf4585849add84cb6a6)
GPU hardware access cannot be guaranteed to complete after unlock memory,
Need perform asynchronous unlock to avoid GPU access the freed MMU page.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit f902173b8ece1f6367c30557498077c569db31ff)
According to board team signal measure result and update trim value as
For USB OTG1, setting 0x5b100010=0X10080802 (default 0X10080807).
For USB OTG2, setting 0x5b110010=0X10080803 (default 0X10080807).
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
TRNG "sample size" (the total number of entropy samples that will be taken
during entropy generation) default / POR value is very conservatively
set to 2500.
Let's set it to 512, the same as the caam driver in U-boot
(drivers/crypto/fsl_caam.c) does.
This solves the issue of RNG performance dropping after a suspend/resume
cycle on parts where caam loses power, since the initial U-boot setttings
are lost and kernel does not restore them when resuming.
Note: when changing the sample size, the self-test parameters need to be
updated accordingly.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
The global driver_data.jr_list contains the list of active job rings
at a given moment.
Picking a JR is done using caam_jr_alloc(), which goes through this list
and chooses the JR with the least number of users ("tfm_count").
During the JR suspend/resume, this list must be updated to reflect that
the JR is no longer available - otherwise caam_jr_alloc() could return
a JR that has been suspended.
While this is rather a theoretical issue (i.e. was not met in practice),
it is a prerequisite for fixing the RNG failure met during suspend/resume.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
With MCU SDK 2.9, there are two copy resource tables published to Linux,
the 1st is vdev0vring0, the 2nd is in rsc-table address.
The 1st is for legacy compatible usage, it will be removed in future
releases. we will only use 2nd new address in future releases.
But at current stage, we still use the 1st one in linux, but we
also need to reserve area for the 2nd one, otherwise when using
linux to kick Mcore, Mcore might overwrite the data used by Linux.
The 2nd table address is as below:
8QXP/DX/DXL: [0x90000000 + 1M – 4KB, 0x90000000 + 1M)
8QM: CM40: [0x90000000 + 1M – 4KB, 0x90000000 + 1M)
CM41: [0x90100000 + 1M – 4KB, 0x90100000 + 1M)
8MQ/MM/MN-evk: [0xb8000000 + 1M – 4KB, 0xb8000000 + 1M)
8MP-evk: [0x55000000 + 1M – 4KB, 0x55000000 + 1M)
Currently only 8DXL and 8MP use MCU SDK 2.9 and others still use MCU
SDK 2.8, but for prepare future update, we update all SoC to reserve
the 2nd table address.
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This is just a workaround for Linux 5.4 Q4 release
to avoid Linux use the memory.
This board only has 1GB memory, the 0xb8000000
exceeds the DRAM, and round back to 0x78000000,
since we not modify Mcore image, so we need to avoid
Linux touch 0x78000000 which might crash the system
and mark mcore ddr demo broken and only support booting mcore image
from U-Boot bootaux.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
subdev_notifier_complete will be called multi times in some cases
due to workaround to support hotplugin-like mechanism, so add checking
media device register status before register new media device.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Remove RGBA format extended before in V4L2 format list due to V4L2
framework support it now.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
There is no RGBA format in V4L2 framework when develop ISI mem2mem
driver, so we add V4L2_PIX_FMT_RGBA in V4L2 framework. But in the
latest kernel version, V4L2 framework add V4L2_PIX_FMT_RGBA32 for
RGBA format, so change use RGBA format define in latest framework.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Remove 4K feature for ISI channel1 due to ISI line buffer limitation
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Add workaround for iMX865 ISI to support 4K because for the ISI line
buffer management, the other chips used a single clock for all the
memories, where as in iMX865, each channel has the corresponding clock
which is used, so need to enable channel1 clock when channel0 chain
buffer enabled.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
When ISI output width more than 2048, it need to use adjacent channel
chain buffer to receive more data. For iMX865, clock for each channel
is independent, so need to enable the adjacent channel clock when the
channel0 chain buffer enabled. This is a workaround for IC issue.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Adjust the LDO trim value based upon the fuse trim value.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
The blk-ctl register allow access to set the MIPI DSI LDO trim value.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Add support for reading fuse to get iMX8mp LDO trim.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Enable support for Hifiberry dacplus audio hats on
iMX8MMini EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit ec6d8970ba79fc7cef371eea888d24e5bd347f2a)
Enable support for IQauidio dacpro audio hats on
iMX8MMini EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit f4122d1b5c3e66c3fe731ea19e6e6e17c2000af6)
Enable support for IQauidio dacplus audio hats on
iMX8MMini EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 95b3f81802fe52fbe66ce6fbb28ae43f78d85f04)
Enable support for Hifiberry dacplus audio hats on
iMX8MNano EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit c0bee3e1d91937b49e22e635f2bca53e8b25f57c)
Enable support for IQauidio dacpro audio hats on
iMX8MNano EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 9ebf35bcd2ce93b3595dee2b3a3f662b70f10088)
Enable support for IQauidio dacplus audio hats on
iMX8MNano EVK.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 0fe19d3f2e949c65ffa636d4971b9f5f463497fd)
Add set_sysclk function to select preferred master input
clock on pcm512x codec, support multiple input system clocks
on SCLK master mode.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 5ca64840578f9dad359d5c2e6821805df68a1608)
Enable imx-pcm512x sound driver as built-in module
for iMX8M EVK support
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 84db7260f5a350f6e3d5418e7a90e8b352aaa183)
ASoC machine sound driver for IQAudio PiDAC plus/pro
Rev3 for iMX SoC, high resolution codec supporting
upto 384khz sample rate on SAI; Include support for
Hifiberry audio hats that uses external oscillators for
dac system clock.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit b52d3587cba2b3db60cf316430478969918fed7a)
We hit the problem with below sequence:
- ci_udc_vbus_session() update vbus_active flag and ci->driver
is valid,
- before calling the ci_hdrc_gadget_connect(),
usb_gadget_udc_stop() is called by application remove gadget
driver,
- ci_udc_vbus_session() will contine do ci_hdrc_gadget_connect() as
gadget_ready is 1, so udc interrupt is enabled, but ci->driver is
NULL.
- USB connection irq generated but ci->driver is NULL.
As udc irq only should be enabled when gadget driver is binded, so
add spinlock to protect the usb irq enable for vbus session handling.
Signed-off-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 72dc8df7920fc24eba0f586c56e900a1643ff2b3)
(cherry picked from commit 0fe900249814f73ecb79c6fb2ae75d46ed9d3a3e)
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 8e43cd16c8bbfe5b7e3c0fc1e7c3ddf738d8db01)
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 2972241b831ed65f641ccdb80b504cadef0ba591)
Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIFv3. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit f252a44da9f90951614c0bf513df6bd4d145e76e)
Due to commit 82586f0aa1c2 (arm64: dts: imx8mp: correct
assigned-clock-rates for video_pll1), so remove unused
2079M clock from imx_pll1443x_tbl.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit b96af227c28b1dfdbdf656de2a77bc4de99136e2)
According to i.MX8MP Architecture Defition Document, the maximum
clock rate comes generated by 'ccm_media_disp2_pix_clk_root' is
160MHz, so 1039.5MHz clock rate is not supported. And besides,
this clock rate will be set to the matched rate with display mode
in lcdif driver, so it is not necessary to set its rate in its
assigned-clock-rates property, and just leave it to be 0.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 0e3556f282466e6b91def024afc815ef77733161)
After using osc_24m for MIPI PHY reference clock source,
the default PHY reference clock rate should be changed
also accordingly. Here choose 12MHz rate for this since
below usual DSI output DDR clock rates can be derived
from 12MHz reference:
891000,
810000,
792000,
648000,
472500,
445500,
390000,
297000,
240000,
189000,
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit b3a420c9cf3fe40c408d4eb58841a0d047c186a4)
Due to commit 26ef2488a2ef (MLK-24998-1 arm64: dts: imx8mp: correct
assigned-clock-rates for video_pll1), default 27MHz dsi PHY reference
clock cannot be derived from 'vide_pll1', so change to use osc_24m
for the clock source and use 12MHz for dsi reference clock rate, since
below usual DDR clock rates can be derived through 12MHz clock rate:
891000,
810000,
792000,
648000,
472500,
445500,
390000,
297000,
240000,
189000,
All these clock rates comes from ADV7535 bridge driver.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit f3915cb61639821fbdcdc9db3cf3a8e0880cbca3)
According to i.MX8MP Architecture Defition Document, the maximum
output frequency generated by video_pll1 is 1190MHz, so correct
its assigned-clock-rates to be 1039.5MHz to meet the spec.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 1dff13053bf83c2d4fb818562a086ad834f2a0bf)
According to i.MX8MP Architecture Defition Document, the maximum
output frequency generated by video_pll1 is 1190MHz, so correct
its assigned-clock-rates to be 1039.5MHz to meet the spec.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit b935595aa00859887a407dc6900763bfd41dfac2)
