2017-05-09 04:19:06 +09:00
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "core_types.h"
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#include "resource.h"
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2017-07-08 06:21:45 +09:00
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#include "custom_float.h"
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2017-05-09 04:19:06 +09:00
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#include "dcn10_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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2017-05-17 05:07:30 +09:00
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#include "dce/dce_hwseq.h"
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2017-05-09 04:19:06 +09:00
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#include "abm.h"
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2017-10-19 05:14:40 +09:00
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#include "dmcu.h"
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2017-12-05 06:58:11 +09:00
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#include "dcn10_optc.h"
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2017-07-06 07:03:04 +09:00
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#include "dcn10/dcn10_dpp.h"
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#include "dcn10/dcn10_mpc.h"
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2017-05-09 04:19:06 +09:00
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#include "timing_generator.h"
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#include "opp.h"
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#include "ipp.h"
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2017-07-08 06:21:45 +09:00
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#include "mpc.h"
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2017-07-05 19:57:49 +09:00
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#include "reg_helper.h"
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2017-09-08 23:25:25 +09:00
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#include "custom_float.h"
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2017-10-06 01:30:14 +09:00
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#include "dcn10_hubp.h"
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2017-10-19 00:59:42 +09:00
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#include "dcn10_hubbub.h"
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2017-11-15 08:12:52 +09:00
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#include "dcn10_cm_common.h"
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2017-05-09 04:19:06 +09:00
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2017-07-05 19:57:49 +09:00
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#define CTX \
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hws->ctx
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#define REG(reg)\
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hws->regs->reg
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2017-05-09 04:19:06 +09:00
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2017-07-05 19:57:49 +09:00
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#undef FN
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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2017-05-09 04:19:06 +09:00
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2017-10-19 00:59:42 +09:00
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#define DTN_INFO_MICRO_SEC(ref_cycle) \
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print_microsec(dc_ctx, ref_cycle)
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2017-08-03 21:59:12 +09:00
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2017-08-03 22:22:14 +09:00
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void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
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{
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static const uint32_t ref_clk_mhz = 48;
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static const unsigned int frac = 10;
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uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
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DTN_INFO("%d.%d \t ",
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us_x10 / frac,
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us_x10 % frac);
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}
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2017-10-19 00:59:42 +09:00
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static void log_mpc_crc(struct dc *dc)
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2017-08-04 12:21:46 +09:00
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{
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2017-10-19 00:59:42 +09:00
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struct dc_context *dc_ctx = dc->ctx;
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struct dce_hwseq *hws = dc->hwseq;
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if (REG(MPC_CRC_RESULT_GB))
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DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
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REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
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if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
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DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
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REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
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2017-08-04 12:21:46 +09:00
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}
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2017-10-19 00:59:42 +09:00
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void dcn10_log_hubbub_state(struct dc *dc)
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2017-08-04 12:21:46 +09:00
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct dcn_hubbub_wm wm;
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int i;
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2017-10-24 05:01:36 +09:00
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hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
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2017-08-04 12:21:46 +09:00
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DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
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"sr_enter \t sr_exit \t dram_clk_change \n");
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for (i = 0; i < 4; i++) {
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struct dcn_hubbub_wm_set *s;
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s = &wm.sets[i];
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DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
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DTN_INFO_MICRO_SEC(s->data_urgent);
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DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
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DTN_INFO_MICRO_SEC(s->sr_enter);
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DTN_INFO_MICRO_SEC(s->sr_exit);
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DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
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DTN_INFO("\n");
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}
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DTN_INFO("\n");
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}
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2017-10-19 00:59:42 +09:00
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void dcn10_log_hw_state(struct dc *dc)
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2017-08-03 21:59:12 +09:00
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct resource_pool *pool = dc->res_pool;
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int i;
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DTN_INFO_BEGIN();
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2017-08-04 12:21:46 +09:00
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dcn10_log_hubbub_state(dc);
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2017-08-03 22:22:14 +09:00
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DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
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"rotation \t mirror \t sw_mode \t "
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"dcc_en \t blank_en \t ttu_dis \t underflow \t "
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2017-08-03 21:59:12 +09:00
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"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
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for (i = 0; i < pool->pipe_count; i++) {
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2017-10-03 03:39:42 +09:00
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struct hubp *hubp = pool->hubps[i];
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2017-08-03 21:59:12 +09:00
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struct dcn_hubp_state s;
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2017-10-03 03:39:42 +09:00
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hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
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2017-08-03 21:59:12 +09:00
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2017-08-03 22:22:14 +09:00
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DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
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"%xh \t %xh \t %xh \t "
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"%d \t %d \t %d \t %xh \t",
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2017-08-03 21:59:12 +09:00
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i,
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s.pixel_format,
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s.inuse_addr_hi,
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s.viewport_width,
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s.viewport_height,
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s.rotation_angle,
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s.h_mirror_en,
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s.sw_mode,
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s.dcc_en,
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s.blank_en,
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s.ttu_disable,
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2017-08-03 22:22:14 +09:00
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s.underflow_status);
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DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
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DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
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DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
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DTN_INFO("\n");
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2017-08-03 21:59:12 +09:00
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}
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DTN_INFO("\n");
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2017-08-17 00:49:07 +09:00
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DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
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"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
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2017-11-02 23:45:12 +09:00
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for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
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2017-08-17 00:49:07 +09:00
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struct timing_generator *tg = pool->timing_generators[i];
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2017-08-19 08:09:57 +09:00
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struct dcn_otg_state s = {0};
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2017-08-17 00:49:07 +09:00
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2017-11-23 06:48:35 +09:00
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optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
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2017-08-17 00:49:07 +09:00
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2017-08-19 08:09:57 +09:00
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//only print if OTG master is enabled
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if ((s.otg_enabled & 1) == 0)
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continue;
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2017-08-17 00:49:07 +09:00
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DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
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"%d \t %d \t %d \t %d \t %d \t %d \t "
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"%d \t %d \t %d \t %d \t %d \t ",
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i,
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s.v_blank_start,
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s.v_blank_end,
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s.v_sync_a_start,
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s.v_sync_a_end,
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s.v_sync_a_pol,
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s.v_total_max,
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s.v_total_min,
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s.h_blank_start,
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s.h_blank_end,
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s.h_sync_a_start,
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s.h_sync_a_end,
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s.h_sync_a_pol,
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s.h_total,
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s.v_total,
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s.underflow_occurred_status);
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DTN_INFO("\n");
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}
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DTN_INFO("\n");
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2017-08-03 21:59:12 +09:00
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log_mpc_crc(dc);
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DTN_INFO_END();
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}
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2017-07-15 03:07:16 +09:00
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2017-05-09 04:19:06 +09:00
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static void enable_power_gating_plane(
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2017-07-05 19:57:49 +09:00
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struct dce_hwseq *hws,
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2017-05-09 04:19:06 +09:00
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bool enable)
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{
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bool force_on = 1; /* disable power gating */
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if (enable)
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force_on = 0;
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/* DCHUBP0/1/2/3 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
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2017-05-09 04:19:06 +09:00
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/* DPP0/1/2/3 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
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REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
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2017-05-09 04:19:06 +09:00
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}
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2017-07-13 11:35:52 +09:00
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static void disable_vga(
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struct dce_hwseq *hws)
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{
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REG_WRITE(D1VGA_CONTROL, 0);
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REG_WRITE(D2VGA_CONTROL, 0);
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REG_WRITE(D3VGA_CONTROL, 0);
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REG_WRITE(D4VGA_CONTROL, 0);
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}
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2017-05-09 04:19:06 +09:00
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static void dpp_pg_control(
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2017-07-05 19:57:49 +09:00
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struct dce_hwseq *hws,
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2017-05-09 04:19:06 +09:00
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unsigned int dpp_inst,
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bool power_on)
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{
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uint32_t power_gate = power_on ? 0 : 1;
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uint32_t pwr_status = power_on ? 0 : 2;
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2017-07-05 19:57:49 +09:00
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if (hws->ctx->dc->debug.disable_dpp_power_gate)
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2017-05-09 04:19:06 +09:00
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return;
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switch (dpp_inst) {
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case 0: /* DPP0 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN1_PG_CONFIG,
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2017-05-09 04:19:06 +09:00
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DOMAIN1_POWER_GATE, power_gate);
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2017-07-05 19:57:49 +09:00
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REG_WAIT(DOMAIN1_PG_STATUS,
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2017-08-04 10:23:04 +09:00
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DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
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1, 1000);
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2017-05-09 04:19:06 +09:00
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break;
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case 1: /* DPP1 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN3_PG_CONFIG,
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2017-05-09 04:19:06 +09:00
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DOMAIN3_POWER_GATE, power_gate);
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2017-07-05 19:57:49 +09:00
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REG_WAIT(DOMAIN3_PG_STATUS,
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2017-08-04 10:23:04 +09:00
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DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
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1, 1000);
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2017-05-09 04:19:06 +09:00
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break;
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case 2: /* DPP2 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN5_PG_CONFIG,
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2017-05-09 04:19:06 +09:00
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DOMAIN5_POWER_GATE, power_gate);
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2017-07-05 19:57:49 +09:00
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REG_WAIT(DOMAIN5_PG_STATUS,
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2017-08-04 10:23:04 +09:00
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DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
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1, 1000);
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2017-05-09 04:19:06 +09:00
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break;
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case 3: /* DPP3 */
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2017-07-05 19:57:49 +09:00
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REG_UPDATE(DOMAIN7_PG_CONFIG,
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2017-05-09 04:19:06 +09:00
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DOMAIN7_POWER_GATE, power_gate);
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2017-07-05 19:57:49 +09:00
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REG_WAIT(DOMAIN7_PG_STATUS,
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2017-08-04 10:23:04 +09:00
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DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
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1, 1000);
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2017-05-09 04:19:06 +09:00
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
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}
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static void hubp_pg_control(
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2017-07-05 19:57:49 +09:00
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struct dce_hwseq *hws,
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2017-05-09 04:19:06 +09:00
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unsigned int hubp_inst,
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bool power_on)
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{
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uint32_t power_gate = power_on ? 0 : 1;
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uint32_t pwr_status = power_on ? 0 : 2;
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|
|
2017-07-05 19:57:49 +09:00
|
|
|
if (hws->ctx->dc->debug.disable_hubp_power_gate)
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
|
|
|
|
switch (hubp_inst) {
|
|
|
|
case 0: /* DCHUBP0 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN0_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN0_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN0_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 1: /* DCHUBP1 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN2_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN2_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN2_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 2: /* DCHUBP2 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN4_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN4_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN4_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 3: /* DCHUBP3 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN6_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN6_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN6_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void power_on_plane(
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws,
|
2017-06-15 07:58:04 +09:00
|
|
|
int plane_id)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-09-21 00:48:47 +09:00
|
|
|
if (REG(DC_IP_REQUEST_CNTL)) {
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 1);
|
|
|
|
dpp_pg_control(hws, plane_id, true);
|
|
|
|
hubp_pg_control(hws, plane_id, true);
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 0);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_DEBUG,
|
|
|
|
"Un-gated front end for pipe %d\n", plane_id);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-08-25 06:40:00 +09:00
|
|
|
static void undo_DEGVIDCN10_253_wa(struct dc *dc)
|
|
|
|
{
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-10-03 03:39:42 +09:00
|
|
|
struct hubp *hubp = dc->res_pool->hubps[0];
|
2017-08-29 05:50:17 +09:00
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
if (!hws->wa_state.DEGVIDCN10_253_applied)
|
2017-08-29 05:50:17 +09:00
|
|
|
return;
|
2017-08-25 06:40:00 +09:00
|
|
|
|
2017-10-03 03:39:42 +09:00
|
|
|
hubp->funcs->set_blank(hubp, true);
|
2017-08-25 06:40:00 +09:00
|
|
|
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 1);
|
|
|
|
|
|
|
|
hubp_pg_control(hws, 0, false);
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 0);
|
2017-11-07 04:40:31 +09:00
|
|
|
|
|
|
|
hws->wa_state.DEGVIDCN10_253_applied = false;
|
2017-08-25 06:40:00 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void apply_DEGVIDCN10_253_wa(struct dc *dc)
|
|
|
|
{
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-10-03 03:39:42 +09:00
|
|
|
struct hubp *hubp = dc->res_pool->hubps[0];
|
2017-11-07 04:40:31 +09:00
|
|
|
int i;
|
2017-08-25 06:40:00 +09:00
|
|
|
|
2017-09-06 01:20:39 +09:00
|
|
|
if (dc->debug.disable_stutter)
|
|
|
|
return;
|
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
if (!hws->wa.DEGVIDCN10_253)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
if (!dc->res_pool->hubps[i]->power_gated)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* all pipe power gated, apply work around to enable stutter. */
|
|
|
|
|
2017-08-25 06:40:00 +09:00
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 1);
|
|
|
|
|
|
|
|
hubp_pg_control(hws, 0, true);
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 0);
|
|
|
|
|
2017-10-03 03:39:42 +09:00
|
|
|
hubp->funcs->set_hubp_blank_en(hubp, false);
|
2017-11-07 04:40:31 +09:00
|
|
|
hws->wa_state.DEGVIDCN10_253_applied = true;
|
2017-08-25 06:40:00 +09:00
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void bios_golden_init(struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
struct dc_bios *bp = dc->ctx->dc_bios;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* initialize dcn global */
|
|
|
|
bp->funcs->enable_disp_power_gating(bp,
|
|
|
|
CONTROLLER_ID_D0, ASIC_PIPE_INIT);
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
/* initialize dcn per pipe */
|
|
|
|
bp->funcs->enable_disp_power_gating(bp,
|
|
|
|
CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-16 06:21:34 +09:00
|
|
|
static void false_optc_underflow_wa(
|
|
|
|
struct dc *dc,
|
|
|
|
const struct dc_stream_state *stream,
|
|
|
|
struct timing_generator *tg)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
bool underflow;
|
|
|
|
|
|
|
|
if (!dc->hwseq->wa.false_optc_underflow)
|
|
|
|
return;
|
|
|
|
|
|
|
|
underflow = tg->funcs->is_optc_underflow_occurred(tg);
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (old_pipe_ctx->stream != stream)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
tg->funcs->set_blank_data_double_buffer(tg, true);
|
|
|
|
|
|
|
|
if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
|
|
|
|
tg->funcs->clear_optc_underflow(tg);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static enum dc_status dcn10_prog_pixclk_crtc_otg(
|
|
|
|
struct pipe_ctx *pipe_ctx,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context,
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
2017-05-09 04:19:06 +09:00
|
|
|
enum dc_color_space color_space;
|
|
|
|
struct tg_color black_color = {0};
|
|
|
|
|
|
|
|
/* by upper caller loop, pipe0 is parent pipe and be called first.
|
|
|
|
* back end is set up by for pipe0. Other children pipe share back end
|
|
|
|
* with pipe 0. No program is needed.
|
|
|
|
*/
|
|
|
|
if (pipe_ctx->top_pipe != NULL)
|
|
|
|
return DC_OK;
|
|
|
|
|
|
|
|
/* TODO check if timing_changed, disable stream if timing changed */
|
|
|
|
|
|
|
|
/* HW program guide assume display already disable
|
|
|
|
* by unplug sequence. OTG assume stop.
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
|
|
|
|
pipe_ctx->clock_source,
|
2017-07-31 04:17:43 +09:00
|
|
|
&pipe_ctx->stream_res.pix_clk_params,
|
2017-05-09 04:19:06 +09:00
|
|
|
&pipe_ctx->pll_settings)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
}
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_timing(
|
|
|
|
pipe_ctx->stream_res.tg,
|
2017-07-26 09:51:26 +09:00
|
|
|
&stream->timing,
|
2017-05-09 04:19:06 +09:00
|
|
|
true);
|
|
|
|
|
|
|
|
#if 0 /* move to after enable_crtc */
|
|
|
|
/* TODO: OPP FMT, ABM. etc. should be done here. */
|
|
|
|
/* or FPGA now. instance 0 only. TODO: move to opp.c */
|
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
|
|
|
|
pipe_ctx->stream_res.opp,
|
2017-05-09 04:19:06 +09:00
|
|
|
&stream->bit_depth_params,
|
|
|
|
&stream->clamping);
|
|
|
|
#endif
|
|
|
|
/* program otg blank color */
|
2017-07-26 09:51:26 +09:00
|
|
|
color_space = stream->output_color_space;
|
2017-05-09 04:19:06 +09:00
|
|
|
color_space_to_black_color(dc, color_space, &black_color);
|
|
|
|
|
2017-12-05 06:58:11 +09:00
|
|
|
if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
|
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank_color(
|
|
|
|
pipe_ctx->stream_res.tg,
|
|
|
|
&black_color);
|
|
|
|
|
|
|
|
if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
|
|
|
|
!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
|
2017-11-16 06:21:34 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
|
|
|
|
hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
|
|
|
|
false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* VTG is within DCHUB command block. DCFCLK is always on */
|
2017-07-31 02:59:26 +09:00
|
|
|
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
|
2017-05-09 04:19:06 +09:00
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO program crtc source select for non-virtual signal*/
|
|
|
|
/* TODO program FMT */
|
|
|
|
/* TODO setup link_enc */
|
|
|
|
/* TODO set stream attributes */
|
|
|
|
/* TODO program audio */
|
|
|
|
/* TODO enable stream if timing changed */
|
|
|
|
/* TODO unblank stream if DP */
|
|
|
|
|
|
|
|
return DC_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void reset_back_end_for_pipe(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-07-31 03:36:12 +09:00
|
|
|
if (pipe_ctx->stream_res.stream_enc == NULL) {
|
2017-05-09 04:19:06 +09:00
|
|
|
pipe_ctx->stream = NULL;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-09-30 05:36:34 +09:00
|
|
|
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
|
|
|
/* DPMS may already disable */
|
|
|
|
if (!pipe_ctx->stream->dpms_off)
|
|
|
|
core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* by upper caller loop, parent pipe: pipe0, will be reset last.
|
|
|
|
* back end share by all pipes and will be disable only when disable
|
|
|
|
* parent pipe.
|
|
|
|
*/
|
|
|
|
if (pipe_ctx->top_pipe == NULL) {
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++)
|
2017-08-26 05:16:10 +09:00
|
|
|
if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (i == dc->res_pool->pipe_count)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pipe_ctx->stream = NULL;
|
2017-08-22 00:46:17 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DEBUG,
|
2017-06-15 07:58:04 +09:00
|
|
|
"Reset back end for pipe %d, tg:%d\n",
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-11-08 01:01:34 +09:00
|
|
|
static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
|
2017-10-25 04:16:38 +09:00
|
|
|
{
|
|
|
|
static bool should_log_hw_state; /* prevent hw state log by default */
|
|
|
|
|
2017-10-27 00:29:54 +09:00
|
|
|
if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
|
2017-10-25 04:16:38 +09:00
|
|
|
if (should_log_hw_state) {
|
|
|
|
dcn10_log_hw_state(dc);
|
|
|
|
}
|
|
|
|
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-24 04:22:47 +09:00
|
|
|
/* trigger HW to start disconnect plane from stream on the next vsync */
|
2017-10-31 06:32:14 +09:00
|
|
|
static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-12-20 06:47:02 +09:00
|
|
|
struct hubp *hubp = pipe_ctx->plane_res.hubp;
|
|
|
|
int dpp_id = pipe_ctx->plane_res.dpp->inst;
|
2017-07-22 06:46:50 +09:00
|
|
|
struct mpc *mpc = dc->res_pool->mpc;
|
2017-12-22 05:38:31 +09:00
|
|
|
int pipe_idx;
|
2017-11-07 06:38:55 +09:00
|
|
|
struct mpc_tree *mpc_tree_params;
|
|
|
|
struct mpcc *mpcc_to_remove = NULL;
|
2017-07-22 06:46:50 +09:00
|
|
|
|
|
|
|
/* look at tree rather than mi here to know if we already reset */
|
2017-12-22 05:38:31 +09:00
|
|
|
for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
|
|
|
|
struct output_pixel_processor *opp = dc->res_pool->opps[pipe_idx];
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-11-07 06:38:55 +09:00
|
|
|
mpc_tree_params = &(opp->mpc_tree_params);
|
2017-12-20 06:47:02 +09:00
|
|
|
mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
|
2017-11-07 06:38:55 +09:00
|
|
|
if (mpcc_to_remove != NULL)
|
2017-07-22 06:46:50 +09:00
|
|
|
break;
|
|
|
|
}
|
2017-11-07 06:38:55 +09:00
|
|
|
|
2017-07-24 04:22:47 +09:00
|
|
|
/*Already reset*/
|
2017-12-22 05:38:31 +09:00
|
|
|
if (pipe_idx == dc->res_pool->pipe_count)
|
2017-07-24 04:22:47 +09:00
|
|
|
return;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-11-07 06:38:55 +09:00
|
|
|
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
|
2017-12-22 05:38:31 +09:00
|
|
|
dc->res_pool->opps[pipe_idx]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
|
2017-10-31 06:32:14 +09:00
|
|
|
|
2017-11-17 05:51:21 +09:00
|
|
|
dc->optimized_required = true;
|
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
if (hubp->funcs->hubp_disconnect)
|
|
|
|
hubp->funcs->hubp_disconnect(hubp);
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-07-15 02:42:23 +09:00
|
|
|
}
|
|
|
|
|
2017-12-20 06:47:02 +09:00
|
|
|
static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
2017-07-24 04:22:47 +09:00
|
|
|
{
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-12-20 06:47:02 +09:00
|
|
|
struct dpp *dpp = pipe_ctx->plane_res.dpp;
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
if (REG(DC_IP_REQUEST_CNTL)) {
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 1);
|
2017-12-20 06:47:02 +09:00
|
|
|
dpp_pg_control(hws, dpp->inst, false);
|
|
|
|
hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
|
2017-10-31 06:32:14 +09:00
|
|
|
dpp->funcs->dpp_reset(dpp);
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 0);
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DEBUG,
|
2017-12-20 06:47:02 +09:00
|
|
|
"Power gated front end %d\n", pipe_ctx->pipe_idx);
|
2017-10-31 06:32:14 +09:00
|
|
|
}
|
|
|
|
}
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
/* disable HW used by plane.
|
|
|
|
* note: cannot disable until disconnect is complete
|
|
|
|
*/
|
|
|
|
static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
2017-10-31 06:32:14 +09:00
|
|
|
{
|
2017-11-07 04:40:31 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-12-20 06:47:02 +09:00
|
|
|
struct hubp *hubp = pipe_ctx->plane_res.hubp;
|
2017-12-21 07:17:40 +09:00
|
|
|
struct dpp *dpp = pipe_ctx->plane_res.dpp;
|
2017-11-07 04:40:31 +09:00
|
|
|
int opp_id = hubp->opp_id;
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-11-16 06:12:19 +09:00
|
|
|
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-12-19 04:09:19 +09:00
|
|
|
hubp->funcs->hubp_clk_cntl(hubp, false);
|
|
|
|
|
2017-12-21 07:17:40 +09:00
|
|
|
dpp->funcs->dpp_dppclk_control(dpp, false, false);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-12-22 05:38:31 +09:00
|
|
|
if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
|
2017-11-07 04:40:31 +09:00
|
|
|
REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
|
|
|
|
OPP_PIPE_CLOCK_EN, 0);
|
2017-10-31 06:32:14 +09:00
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
hubp->power_gated = true;
|
2017-11-17 05:51:21 +09:00
|
|
|
dc->optimized_required = false; /* We're powering off, no need to optimize */
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-12-20 06:47:02 +09:00
|
|
|
plane_atomic_power_down(dc, pipe_ctx);
|
2017-11-16 06:12:19 +09:00
|
|
|
|
|
|
|
pipe_ctx->stream = NULL;
|
|
|
|
memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
|
|
|
|
memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
|
|
|
|
pipe_ctx->top_pipe = NULL;
|
|
|
|
pipe_ctx->bottom_pipe = NULL;
|
|
|
|
pipe_ctx->plane_state = NULL;
|
2017-11-07 04:40:31 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
|
|
|
|
return;
|
|
|
|
|
|
|
|
plane_atomic_disable(dc, pipe_ctx);
|
|
|
|
|
|
|
|
apply_DEGVIDCN10_253_wa(dc);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
2017-11-07 04:40:31 +09:00
|
|
|
"Power down front end %d\n",
|
|
|
|
pipe_ctx->pipe_idx);
|
2017-07-24 04:22:47 +09:00
|
|
|
}
|
|
|
|
|
2017-10-21 03:12:35 +09:00
|
|
|
static void dcn10_init_hw(struct dc *dc)
|
|
|
|
{
|
2017-11-17 05:34:50 +09:00
|
|
|
int i;
|
2017-10-21 03:12:35 +09:00
|
|
|
struct abm *abm = dc->res_pool->abm;
|
|
|
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-11-03 02:24:20 +09:00
|
|
|
struct dc_bios *dcb = dc->ctx->dc_bios;
|
|
|
|
struct dc_state *context = dc->current_state;
|
2017-10-21 03:12:35 +09:00
|
|
|
|
|
|
|
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
|
|
|
REG_WRITE(REFCLK_CNTL, 0);
|
|
|
|
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
|
|
|
|
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
|
|
|
|
|
|
|
|
if (!dc->debug.disable_clock_gate) {
|
|
|
|
/* enable all DCN clock gating */
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
|
|
|
|
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
|
|
|
|
|
|
|
|
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
enable_power_gating_plane(dc->hwseq, true);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* end of FPGA. Below if real ASIC */
|
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
if (!dcb->funcs->is_accelerated_mode(dcb)) {
|
|
|
|
bios_golden_init(dc);
|
|
|
|
disable_vga(dc->hwseq);
|
|
|
|
}
|
2017-10-21 03:12:35 +09:00
|
|
|
|
|
|
|
for (i = 0; i < dc->link_count; i++) {
|
|
|
|
/* Power up AND update implementation according to the
|
|
|
|
* required signal (which may be different from the
|
|
|
|
* default signal on connector).
|
|
|
|
*/
|
|
|
|
struct dc_link *link = dc->links[i];
|
|
|
|
|
2017-09-27 08:45:43 +09:00
|
|
|
if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
|
|
|
|
dc->hwss.edp_power_control(link, true);
|
|
|
|
|
2017-10-21 03:12:35 +09:00
|
|
|
link->link_enc->funcs->hw_init(link->link_enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
if (tg->funcs->is_tg_enabled(tg))
|
|
|
|
tg->funcs->lock(tg);
|
|
|
|
}
|
2017-10-21 03:12:35 +09:00
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
/* Blank controller using driver code instead of
|
|
|
|
* command table.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
|
|
|
|
|
|
|
if (tg->funcs->is_tg_enabled(tg)) {
|
|
|
|
tg->funcs->set_blank(tg, true);
|
|
|
|
hwss_wait_for_blank_complete(tg);
|
|
|
|
}
|
|
|
|
}
|
2017-10-21 03:12:35 +09:00
|
|
|
|
2017-11-17 05:34:50 +09:00
|
|
|
/* Reset all MPCC muxes */
|
|
|
|
dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
|
2017-11-07 06:38:55 +09:00
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
2017-11-15 02:40:20 +09:00
|
|
|
struct hubp *hubp = dc->res_pool->hubps[i];
|
2017-12-20 06:47:02 +09:00
|
|
|
struct dpp *dpp = dc->res_pool->dpps[i];
|
2017-11-15 02:40:20 +09:00
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
pipe_ctx->stream_res.tg = tg;
|
|
|
|
pipe_ctx->pipe_idx = i;
|
2017-11-15 02:40:20 +09:00
|
|
|
|
|
|
|
pipe_ctx->plane_res.hubp = hubp;
|
2017-12-20 06:47:02 +09:00
|
|
|
pipe_ctx->plane_res.dpp = dpp;
|
|
|
|
pipe_ctx->plane_res.mpcc_inst = dpp->inst;
|
|
|
|
hubp->mpcc_id = dpp->inst;
|
2017-11-17 05:34:50 +09:00
|
|
|
hubp->opp_id = 0xf;
|
2017-11-15 02:40:20 +09:00
|
|
|
hubp->power_gated = false;
|
2017-11-03 02:24:20 +09:00
|
|
|
|
2017-11-25 07:51:34 +09:00
|
|
|
dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
|
|
|
|
dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
|
2017-12-20 06:47:02 +09:00
|
|
|
dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
|
2017-11-22 07:51:50 +09:00
|
|
|
pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
|
2017-11-16 06:12:19 +09:00
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
plane_atomic_disconnect(dc, pipe_ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
|
|
|
|
|
|
|
if (tg->funcs->is_tg_enabled(tg))
|
|
|
|
tg->funcs->unlock(tg);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
dcn10_disable_plane(dc, pipe_ctx);
|
2017-10-31 02:35:04 +09:00
|
|
|
|
2017-11-03 02:24:20 +09:00
|
|
|
pipe_ctx->stream_res.tg = NULL;
|
|
|
|
pipe_ctx->plane_res.hubp = NULL;
|
|
|
|
|
2017-10-31 02:35:04 +09:00
|
|
|
tg->funcs->tg_init(tg);
|
2017-10-21 03:12:35 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->audio_count; i++) {
|
|
|
|
struct audio *audio = dc->res_pool->audios[i];
|
|
|
|
|
|
|
|
audio->funcs->hw_init(audio);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (abm != NULL) {
|
|
|
|
abm->funcs->init_backlight(abm);
|
|
|
|
abm->funcs->abm_init(abm);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dmcu != NULL)
|
|
|
|
dmcu->funcs->dmcu_init(dmcu);
|
|
|
|
|
|
|
|
/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
|
|
|
|
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
|
|
|
|
|
|
|
|
if (!dc->debug.disable_clock_gate) {
|
|
|
|
/* enable all DCN clock gating */
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
|
|
|
|
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
|
|
|
|
|
|
|
|
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
enable_power_gating_plane(dc->hwseq, true);
|
|
|
|
}
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
static void reset_hw_ctx_wrap(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
/* Reset Back End*/
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
|
|
|
struct pipe_ctx *pipe_ctx_old =
|
2017-08-26 05:16:10 +09:00
|
|
|
&dc->current_state->res_ctx.pipe_ctx[i];
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (!pipe_ctx_old->stream)
|
|
|
|
continue;
|
|
|
|
|
2017-09-23 05:06:04 +09:00
|
|
|
if (pipe_ctx_old->top_pipe)
|
|
|
|
continue;
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (!pipe_ctx->stream ||
|
2017-09-06 04:50:48 +09:00
|
|
|
pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
|
|
|
|
struct clock_source *old_clk = pipe_ctx_old->clock_source;
|
|
|
|
|
2017-08-26 05:16:10 +09:00
|
|
|
reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
|
2017-09-06 04:50:48 +09:00
|
|
|
if (old_clk)
|
|
|
|
old_clk->funcs->cs_power_down(old_clk);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-09-06 04:50:48 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
static bool patch_address_for_sbs_tb_stereo(
|
|
|
|
struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-05-09 04:19:06 +09:00
|
|
|
bool sec_split = pipe_ctx->top_pipe &&
|
2017-07-27 22:55:38 +09:00
|
|
|
pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
|
|
|
|
if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
|
2017-07-26 09:51:26 +09:00
|
|
|
(pipe_ctx->stream->timing.timing_3d_format ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TIMING_3D_FORMAT_SIDE_BY_SIDE ||
|
2017-07-26 09:51:26 +09:00
|
|
|
pipe_ctx->stream->timing.timing_3d_format ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
|
2017-07-27 22:55:38 +09:00
|
|
|
*addr = plane_state->address.grph_stereo.left_addr;
|
|
|
|
plane_state->address.grph_stereo.left_addr =
|
|
|
|
plane_state->address.grph_stereo.right_addr;
|
2017-05-09 04:19:06 +09:00
|
|
|
return true;
|
2017-06-29 03:36:25 +09:00
|
|
|
} else {
|
2017-07-26 09:51:26 +09:00
|
|
|
if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
|
|
|
|
plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
|
|
|
|
plane_state->address.grph_stereo.right_addr =
|
|
|
|
plane_state->address.grph_stereo.left_addr;
|
2017-06-29 03:36:25 +09:00
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-08-05 04:42:36 +09:00
|
|
|
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
bool addr_patched = false;
|
|
|
|
PHYSICAL_ADDRESS_LOC addr;
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state == NULL)
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
|
2017-10-03 03:39:42 +09:00
|
|
|
pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
|
|
|
|
pipe_ctx->plane_res.hubp,
|
2017-07-27 22:55:38 +09:00
|
|
|
&plane_state->address,
|
|
|
|
plane_state->flip_immediate);
|
|
|
|
plane_state->status.requested_address = plane_state->address;
|
2017-05-09 04:19:06 +09:00
|
|
|
if (addr_patched)
|
2017-07-27 22:55:38 +09:00
|
|
|
pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-11-01 05:27:59 +09:00
|
|
|
static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
|
|
|
|
const struct dc_plane_state *plane_state)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-10-06 05:47:49 +09:00
|
|
|
struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
|
2017-07-11 03:04:21 +09:00
|
|
|
const struct dc_transfer_func *tf = NULL;
|
2017-05-09 04:19:06 +09:00
|
|
|
bool result = true;
|
|
|
|
|
2017-10-06 05:47:49 +09:00
|
|
|
if (dpp_base == NULL)
|
2017-05-09 04:19:06 +09:00
|
|
|
return false;
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state->in_transfer_func)
|
|
|
|
tf = plane_state->in_transfer_func;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-12-21 00:07:42 +09:00
|
|
|
if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
|
2017-11-01 05:27:59 +09:00
|
|
|
dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
|
2017-05-17 05:07:30 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (tf == NULL)
|
2017-11-01 04:23:57 +09:00
|
|
|
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
|
2017-07-11 03:04:21 +09:00
|
|
|
else if (tf->type == TF_TYPE_PREDEFINED) {
|
|
|
|
switch (tf->tf) {
|
2017-05-09 04:19:06 +09:00
|
|
|
case TRANSFER_FUNCTION_SRGB:
|
2017-11-01 05:27:59 +09:00
|
|
|
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_BT709:
|
2017-11-01 05:27:59 +09:00
|
|
|
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_LINEAR:
|
2017-11-01 05:27:59 +09:00
|
|
|
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_PQ:
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
2017-07-11 03:04:21 +09:00
|
|
|
} else if (tf->type == TF_TYPE_BYPASS) {
|
2017-11-01 04:23:57 +09:00
|
|
|
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
|
2017-05-09 04:19:06 +09:00
|
|
|
} else {
|
|
|
|
/*TF_TYPE_DISTRIBUTED_POINTS*/
|
|
|
|
result = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-11-01 05:27:59 +09:00
|
|
|
static bool
|
|
|
|
dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
|
|
|
|
const struct dc_stream_state *stream)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-10-06 05:47:49 +09:00
|
|
|
struct dpp *dpp = pipe_ctx->plane_res.dpp;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-10-06 05:47:49 +09:00
|
|
|
if (dpp == NULL)
|
2017-05-10 03:45:54 +09:00
|
|
|
return false;
|
|
|
|
|
2017-10-06 05:47:49 +09:00
|
|
|
dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-26 09:51:26 +09:00
|
|
|
if (stream->out_transfer_func &&
|
2017-11-01 05:27:59 +09:00
|
|
|
stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
|
|
|
|
stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
|
2017-11-01 04:23:57 +09:00
|
|
|
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
|
2017-11-11 05:40:52 +09:00
|
|
|
|
|
|
|
/* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
|
|
|
|
* update.
|
|
|
|
*/
|
2017-11-15 08:12:52 +09:00
|
|
|
else if (cm_helper_translate_curve_to_hw_format(
|
2017-11-11 05:40:52 +09:00
|
|
|
stream->out_transfer_func,
|
2017-11-15 08:12:52 +09:00
|
|
|
&dpp->regamma_params, false)) {
|
2017-11-11 05:40:52 +09:00
|
|
|
dpp->funcs->dpp_program_regamma_pwl(
|
|
|
|
dpp,
|
|
|
|
&dpp->regamma_params, OPP_REGAMMA_USER);
|
|
|
|
} else
|
2017-11-01 04:23:57 +09:00
|
|
|
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_pipe_control_lock(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe,
|
|
|
|
bool lock)
|
|
|
|
{
|
2017-10-03 03:39:42 +09:00
|
|
|
struct hubp *hubp = NULL;
|
|
|
|
hubp = dc->res_pool->hubps[pipe->pipe_idx];
|
2017-05-09 04:19:06 +09:00
|
|
|
/* use TG master update lock to lock everything on the TG
|
|
|
|
* therefore only top pipe need to lock
|
|
|
|
*/
|
|
|
|
if (pipe->top_pipe)
|
|
|
|
return;
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (lock)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
else
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool wait_for_reset_trigger_to_occur(
|
|
|
|
struct dc_context *dc_ctx,
|
|
|
|
struct timing_generator *tg)
|
|
|
|
{
|
|
|
|
bool rc = false;
|
|
|
|
|
|
|
|
/* To avoid endless loop we wait at most
|
|
|
|
* frames_to_wait_on_triggered_reset frames for the reset to occur. */
|
|
|
|
const uint32_t frames_to_wait_on_triggered_reset = 10;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
|
|
|
|
|
|
|
|
if (!tg->funcs->is_counter_moving(tg)) {
|
|
|
|
DC_ERROR("TG counter is not moving!\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tg->funcs->did_triggered_reset_occur(tg)) {
|
|
|
|
rc = true;
|
|
|
|
/* usually occurs at i=1 */
|
|
|
|
DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
|
|
|
|
i);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait for one frame. */
|
|
|
|
tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
|
|
|
|
tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (false == rc)
|
|
|
|
DC_ERROR("GSL: Timeout on reset trigger!\n");
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_enable_timing_synchronization(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
int group_index,
|
|
|
|
int group_size,
|
|
|
|
struct pipe_ctx *grouped_pipes[])
|
|
|
|
{
|
|
|
|
struct dc_context *dc_ctx = dc->ctx;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Setting up OTG reset trigger\n");
|
|
|
|
|
|
|
|
for (i = 1; i < group_size; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
|
2017-10-18 04:29:22 +09:00
|
|
|
grouped_pipes[i]->stream_res.tg,
|
|
|
|
grouped_pipes[0]->stream_res.tg->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
DC_SYNC_INFO("Waiting for trigger\n");
|
|
|
|
|
|
|
|
/* Need to get only check 1 pipe for having reset as all the others are
|
|
|
|
* synchronized. Look at last pipe programmed to reset.
|
|
|
|
*/
|
2017-10-18 04:29:22 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = 1; i < group_size; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
|
|
|
|
grouped_pipes[i]->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
DC_SYNC_INFO("Sync complete\n");
|
|
|
|
}
|
|
|
|
|
2017-10-18 04:29:22 +09:00
|
|
|
static void dcn10_enable_per_frame_crtc_position_reset(
|
|
|
|
struct dc *dc,
|
|
|
|
int group_size,
|
|
|
|
struct pipe_ctx *grouped_pipes[])
|
|
|
|
{
|
|
|
|
struct dc_context *dc_ctx = dc->ctx;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Setting up\n");
|
|
|
|
for (i = 0; i < group_size; i++)
|
|
|
|
grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
|
|
|
|
grouped_pipes[i]->stream_res.tg,
|
|
|
|
grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
|
|
|
|
&grouped_pipes[i]->stream->triggered_crtc_reset);
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Waiting for trigger\n");
|
|
|
|
|
2017-12-19 00:34:56 +09:00
|
|
|
for (i = 0; i < group_size; i++)
|
2017-10-18 04:29:22 +09:00
|
|
|
wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Multi-display sync is complete\n");
|
|
|
|
}
|
|
|
|
|
2017-11-08 01:01:34 +09:00
|
|
|
/*static void print_rq_dlg_ttu(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *core_dc,
|
2017-06-08 02:53:30 +09:00
|
|
|
struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML TTU Output parameters [%d] ==============\n"
|
|
|
|
"qos_level_low_wm: %d, \n"
|
|
|
|
"qos_level_high_wm: %d, \n"
|
|
|
|
"min_ttu_vblank: %d, \n"
|
|
|
|
"qos_level_flip: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_l: %d, \n"
|
|
|
|
"qos_level_fixed_l: %d, \n"
|
|
|
|
"qos_ramp_disable_l: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_pre_l: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_c: %d, \n"
|
|
|
|
"qos_level_fixed_c: %d, \n"
|
|
|
|
"qos_ramp_disable_c: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_pre_c: %d\n"
|
|
|
|
"=============================================================\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_low_wm,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_high_wm,
|
|
|
|
pipe_ctx->ttu_regs.min_ttu_vblank,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_flip,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_fixed_l,
|
|
|
|
pipe_ctx->ttu_regs.qos_ramp_disable_l,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_fixed_c,
|
|
|
|
pipe_ctx->ttu_regs.qos_ramp_disable_c,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML DLG Output parameters [%d] ==============\n"
|
|
|
|
"refcyc_h_blank_end: %d, \n"
|
|
|
|
"dlg_vblank_end: %d, \n"
|
|
|
|
"min_dst_y_next_start: %d, \n"
|
|
|
|
"refcyc_per_htotal: %d, \n"
|
|
|
|
"refcyc_x_after_scaler: %d, \n"
|
|
|
|
"dst_y_after_scaler: %d, \n"
|
|
|
|
"dst_y_prefetch: %d, \n"
|
|
|
|
"dst_y_per_vm_vblank: %d, \n"
|
|
|
|
"dst_y_per_row_vblank: %d, \n"
|
|
|
|
"ref_freq_to_pix_freq: %d, \n"
|
|
|
|
"vratio_prefetch: %d, \n"
|
|
|
|
"refcyc_per_pte_group_vblank_l: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_vblank_l: %d, \n"
|
|
|
|
"dst_y_per_pte_row_nom_l: %d, \n"
|
|
|
|
"refcyc_per_pte_group_nom_l: %d, \n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_h_blank_end,
|
|
|
|
pipe_ctx->dlg_regs.dlg_vblank_end,
|
|
|
|
pipe_ctx->dlg_regs.min_dst_y_next_start,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_htotal,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_x_after_scaler,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_after_scaler,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_prefetch,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_row_vblank,
|
|
|
|
pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
|
|
|
|
pipe_ctx->dlg_regs.vratio_prefetch,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\ndst_y_per_meta_row_nom_l: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_nom_l: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_pre_l: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_l: %d, \n"
|
|
|
|
"vratio_prefetch_c: %d, \n"
|
|
|
|
"refcyc_per_pte_group_vblank_c: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_vblank_c: %d, \n"
|
|
|
|
"dst_y_per_pte_row_nom_c: %d, \n"
|
|
|
|
"refcyc_per_pte_group_nom_c: %d, \n"
|
|
|
|
"dst_y_per_meta_row_nom_c: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_nom_c: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_pre_c: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_c: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
|
|
|
|
pipe_ctx->dlg_regs.vratio_prefetch_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML RQ Output parameters [%d] ==============\n"
|
|
|
|
"chunk_size: %d \n"
|
|
|
|
"min_chunk_size: %d \n"
|
|
|
|
"meta_chunk_size: %d \n"
|
|
|
|
"min_meta_chunk_size: %d \n"
|
|
|
|
"dpte_group_size: %d \n"
|
|
|
|
"mpte_group_size: %d \n"
|
|
|
|
"swath_height: %d \n"
|
|
|
|
"pte_row_height_linear: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.swath_height,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
|
|
|
|
);
|
|
|
|
}
|
2017-11-08 01:01:34 +09:00
|
|
|
*/
|
2017-06-08 02:53:30 +09:00
|
|
|
|
2017-11-09 04:50:06 +09:00
|
|
|
static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
|
|
|
|
struct vm_system_aperture_param *apt,
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
PHYSICAL_ADDRESS_LOC physical_page_number;
|
|
|
|
uint32_t logical_addr_low;
|
|
|
|
uint32_t logical_addr_high;
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
|
|
|
|
PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
|
|
|
|
PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
|
|
|
LOGICAL_ADDR, &logical_addr_low);
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
|
|
|
LOGICAL_ADDR, &logical_addr_high);
|
|
|
|
|
|
|
|
apt->sys_default.quad_part = physical_page_number.quad_part << 12;
|
|
|
|
apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
|
|
|
|
apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Temporary read settings, future will get values from kmd directly */
|
|
|
|
static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
|
|
|
|
struct vm_context0_param *vm0,
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
PHYSICAL_ADDRESS_LOC fb_base;
|
|
|
|
PHYSICAL_ADDRESS_LOC fb_offset;
|
|
|
|
uint32_t fb_base_value;
|
|
|
|
uint32_t fb_offset_value;
|
|
|
|
|
|
|
|
REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
|
|
|
|
REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
|
|
|
|
PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
|
|
|
PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
|
|
|
|
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
|
|
|
|
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
|
|
|
|
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
|
|
|
|
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
|
|
|
|
PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
|
|
|
|
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
|
|
|
|
PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
|
|
|
|
* Therefore we need to do
|
|
|
|
* DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
|
|
|
|
* - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
|
|
|
|
*/
|
|
|
|
fb_base.quad_part = (uint64_t)fb_base_value << 24;
|
|
|
|
fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
|
|
|
|
vm0->pte_base.quad_part += fb_base.quad_part;
|
|
|
|
vm0->pte_base.quad_part -= fb_offset.quad_part;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
|
|
|
|
{
|
|
|
|
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
|
|
|
|
struct vm_system_aperture_param apt = { {{ 0 } } };
|
|
|
|
struct vm_context0_param vm0 = { { { 0 } } };
|
|
|
|
|
|
|
|
mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
|
|
|
|
mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
|
|
|
|
|
|
|
|
hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
|
|
|
|
hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
|
|
|
|
}
|
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
static void dcn10_enable_plane(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
undo_DEGVIDCN10_253_wa(dc);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
power_on_plane(dc->hwseq,
|
2017-12-20 06:47:02 +09:00
|
|
|
pipe_ctx->plane_res.hubp->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-06-08 02:53:30 +09:00
|
|
|
/* enable DCFCLK current DCHUB */
|
2017-12-19 04:09:19 +09:00
|
|
|
pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
|
2017-07-13 00:54:10 +09:00
|
|
|
|
|
|
|
/* make sure OPP_PIPE_CLOCK_EN = 1 */
|
2017-07-31 02:59:26 +09:00
|
|
|
REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
|
2017-07-13 00:54:10 +09:00
|
|
|
OPP_PIPE_CLOCK_EN, 1);
|
2017-06-08 02:53:30 +09:00
|
|
|
|
2017-11-08 01:01:34 +09:00
|
|
|
/* TODO: enable/disable in dm as per update type.
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state) {
|
2017-09-01 05:08:51 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
2017-06-08 02:53:30 +09:00
|
|
|
"Pipe:%d 0x%x: addr hi:0x%x, "
|
|
|
|
"addr low:0x%x, "
|
|
|
|
"src: %d, %d, %d,"
|
|
|
|
" %d; dst: %d, %d, %d, %d;\n",
|
2017-05-09 04:19:06 +09:00
|
|
|
pipe_ctx->pipe_idx,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state,
|
|
|
|
plane_state->address.grph.addr.high_part,
|
|
|
|
plane_state->address.grph.addr.low_part,
|
|
|
|
plane_state->src_rect.x,
|
|
|
|
plane_state->src_rect.y,
|
|
|
|
plane_state->src_rect.width,
|
|
|
|
plane_state->src_rect.height,
|
|
|
|
plane_state->dst_rect.x,
|
|
|
|
plane_state->dst_rect.y,
|
|
|
|
plane_state->dst_rect.width,
|
|
|
|
plane_state->dst_rect.height);
|
2017-06-08 02:53:30 +09:00
|
|
|
|
2017-09-01 05:08:51 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
2017-10-13 11:45:25 +09:00
|
|
|
"Pipe %d: width, height, x, y format:%d\n"
|
2017-06-08 02:53:30 +09:00
|
|
|
"viewport:%d, %d, %d, %d\n"
|
|
|
|
"recout: %d, %d, %d, %d\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
2017-10-13 11:45:25 +09:00
|
|
|
plane_state->format,
|
2017-07-31 00:51:21 +09:00
|
|
|
pipe_ctx->plane_res.scl_data.viewport.width,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.height,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.x,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.y,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.width,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.height,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.x,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.y);
|
2017-06-08 02:53:30 +09:00
|
|
|
print_rq_dlg_ttu(dc, pipe_ctx);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-11-08 01:01:34 +09:00
|
|
|
*/
|
2017-11-09 04:50:06 +09:00
|
|
|
if (dc->config.gpu_vm_support)
|
|
|
|
dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
|
2017-08-04 03:20:14 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-12-16 07:58:45 +09:00
|
|
|
int i = 0;
|
2017-10-06 05:47:49 +09:00
|
|
|
struct dpp_grph_csc_adjustment adjust;
|
2017-05-09 04:19:06 +09:00
|
|
|
memset(&adjust, 0, sizeof(adjust));
|
|
|
|
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
|
|
|
|
|
|
|
|
|
2017-07-26 09:51:26 +09:00
|
|
|
if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
|
2017-12-16 07:58:45 +09:00
|
|
|
for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
|
|
|
|
adjust.temperature_matrix[i] =
|
|
|
|
pipe_ctx->stream->gamut_remap_matrix.matrix[i];
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-10-06 05:47:49 +09:00
|
|
|
pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-06-29 06:21:42 +09:00
|
|
|
|
|
|
|
static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
|
|
|
|
enum dc_color_space colorspace,
|
|
|
|
uint16_t *matrix)
|
|
|
|
{
|
2017-10-24 06:02:02 +09:00
|
|
|
if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
|
2017-11-02 05:48:52 +09:00
|
|
|
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
|
2017-12-02 02:42:18 +09:00
|
|
|
pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
|
2017-10-28 04:28:38 +09:00
|
|
|
} else {
|
2017-11-02 05:48:52 +09:00
|
|
|
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
|
|
|
|
pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
|
2017-06-29 06:21:42 +09:00
|
|
|
}
|
|
|
|
}
|
2017-10-20 02:41:30 +09:00
|
|
|
|
2017-11-02 05:48:52 +09:00
|
|
|
static void program_output_csc(struct dc *dc,
|
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
enum dc_color_space colorspace,
|
|
|
|
uint16_t *matrix,
|
|
|
|
int opp_id)
|
|
|
|
{
|
|
|
|
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
|
|
|
|
program_csc_matrix(pipe_ctx,
|
|
|
|
colorspace,
|
|
|
|
matrix);
|
|
|
|
}
|
|
|
|
|
2017-05-12 06:15:14 +09:00
|
|
|
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
|
|
|
|
return true;
|
|
|
|
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-06-06 04:08:10 +09:00
|
|
|
static bool is_rgb_cspace(enum dc_color_space output_color_space)
|
|
|
|
{
|
|
|
|
switch (output_color_space) {
|
|
|
|
case COLOR_SPACE_SRGB:
|
|
|
|
case COLOR_SPACE_SRGB_LIMITED:
|
|
|
|
case COLOR_SPACE_2020_RGB_FULLRANGE:
|
|
|
|
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
|
|
|
|
case COLOR_SPACE_ADOBERGB:
|
|
|
|
return true;
|
|
|
|
case COLOR_SPACE_YCBCR601:
|
|
|
|
case COLOR_SPACE_YCBCR709:
|
|
|
|
case COLOR_SPACE_YCBCR601_LIMITED:
|
|
|
|
case COLOR_SPACE_YCBCR709_LIMITED:
|
|
|
|
case COLOR_SPACE_2020_YCBCR:
|
|
|
|
return false;
|
|
|
|
default:
|
|
|
|
/* Add a case to switch */
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-07 03:27:49 +09:00
|
|
|
static void dcn10_get_surface_visual_confirm_color(
|
|
|
|
const struct pipe_ctx *pipe_ctx,
|
|
|
|
struct tg_color *color)
|
|
|
|
{
|
|
|
|
uint32_t color_value = MAX_TG_COLOR_VALUE;
|
|
|
|
|
2017-07-31 00:51:21 +09:00
|
|
|
switch (pipe_ctx->plane_res.scl_data.format) {
|
2017-07-07 03:27:49 +09:00
|
|
|
case PIXEL_FORMAT_ARGB8888:
|
|
|
|
/* set boarder color to red */
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PIXEL_FORMAT_ARGB2101010:
|
|
|
|
/* set boarder color to blue */
|
|
|
|
color->color_b_cb = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_420BPP8:
|
|
|
|
/* set boarder color to green */
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_420BPP10:
|
|
|
|
/* set boarder color to yellow */
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_FP16:
|
|
|
|
/* set boarder color to white */
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
color->color_b_cb = color_value;
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-20 02:41:30 +09:00
|
|
|
static uint16_t fixed_point_to_int_frac(
|
|
|
|
struct fixed31_32 arg,
|
|
|
|
uint8_t integer_bits,
|
|
|
|
uint8_t fractional_bits)
|
|
|
|
{
|
|
|
|
int32_t numerator;
|
|
|
|
int32_t divisor = 1 << fractional_bits;
|
|
|
|
|
|
|
|
uint16_t result;
|
|
|
|
|
|
|
|
uint16_t d = (uint16_t)dal_fixed31_32_floor(
|
|
|
|
dal_fixed31_32_abs(
|
|
|
|
arg));
|
|
|
|
|
|
|
|
if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
|
|
|
|
numerator = (uint16_t)dal_fixed31_32_floor(
|
|
|
|
dal_fixed31_32_mul_int(
|
|
|
|
arg,
|
|
|
|
divisor));
|
|
|
|
else {
|
|
|
|
numerator = dal_fixed31_32_floor(
|
|
|
|
dal_fixed31_32_sub(
|
|
|
|
dal_fixed31_32_from_int(
|
|
|
|
1LL << integer_bits),
|
|
|
|
dal_fixed31_32_recip(
|
|
|
|
dal_fixed31_32_from_int(
|
|
|
|
divisor))));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (numerator >= 0)
|
|
|
|
result = (uint16_t)numerator;
|
|
|
|
else
|
|
|
|
result = (uint16_t)(
|
|
|
|
(1 << (integer_bits + fractional_bits + 1)) + numerator);
|
|
|
|
|
|
|
|
if ((result != 0) && dal_fixed31_32_lt(
|
|
|
|
arg, dal_fixed31_32_zero))
|
|
|
|
result |= 1 << (integer_bits + fractional_bits);
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
|
|
|
|
const struct dc_plane_state *plane_state)
|
|
|
|
{
|
|
|
|
if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
|
|
|
|
&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
|
|
|
|
&& plane_state->input_csc_color_matrix.enable_adjustment
|
|
|
|
&& plane_state->coeff_reduction_factor.value != 0) {
|
|
|
|
bias_and_scale->scale_blue = fixed_point_to_int_frac(
|
|
|
|
dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
|
|
|
|
dal_fixed31_32_from_fraction(256, 255)),
|
|
|
|
2,
|
|
|
|
13);
|
|
|
|
bias_and_scale->scale_red = bias_and_scale->scale_blue;
|
|
|
|
bias_and_scale->scale_green = bias_and_scale->scale_blue;
|
|
|
|
} else {
|
|
|
|
bias_and_scale->scale_blue = 0x2000;
|
|
|
|
bias_and_scale->scale_red = 0x2000;
|
|
|
|
bias_and_scale->scale_green = 0x2000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-10-20 02:41:30 +09:00
|
|
|
struct dc_bias_and_scale bns_params = {0};
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-10-20 02:41:30 +09:00
|
|
|
// program the input csc
|
2017-11-01 04:23:57 +09:00
|
|
|
dpp->funcs->dpp_setup(dpp,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->format,
|
2017-10-20 02:41:30 +09:00
|
|
|
EXPANSION_MODE_ZERO,
|
|
|
|
plane_state->input_csc_color_matrix,
|
|
|
|
COLOR_SPACE_YCBCR601_LIMITED);
|
|
|
|
|
|
|
|
//set scale and bias registers
|
|
|
|
build_prescale_params(&bns_params, plane_state);
|
2017-11-01 04:23:57 +09:00
|
|
|
if (dpp->funcs->dpp_program_bias_and_scale)
|
|
|
|
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
|
2017-11-09 07:24:54 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
struct hubp *hubp = pipe_ctx->plane_res.hubp;
|
2017-11-07 06:38:55 +09:00
|
|
|
struct mpcc_blnd_cfg blnd_cfg;
|
|
|
|
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
|
|
|
|
int mpcc_id;
|
|
|
|
struct mpcc *new_mpcc;
|
|
|
|
struct mpc *mpc = dc->res_pool->mpc;
|
|
|
|
struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
|
2017-11-09 07:24:54 +09:00
|
|
|
|
|
|
|
/* TODO: proper fix once fpga works */
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.surface_visual_confirm)
|
2017-07-22 06:46:50 +09:00
|
|
|
dcn10_get_surface_visual_confirm_color(
|
2017-11-07 06:38:55 +09:00
|
|
|
pipe_ctx, &blnd_cfg.black_color);
|
2017-06-02 07:35:54 +09:00
|
|
|
else
|
2017-07-22 06:46:50 +09:00
|
|
|
color_space_to_black_color(
|
|
|
|
dc, pipe_ctx->stream->output_color_space,
|
2017-11-07 06:38:55 +09:00
|
|
|
&blnd_cfg.black_color);
|
|
|
|
|
|
|
|
if (per_pixel_alpha)
|
|
|
|
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
|
|
|
|
else
|
|
|
|
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
|
|
|
|
|
|
|
|
blnd_cfg.overlap_only = false;
|
|
|
|
blnd_cfg.global_alpha = 0xff;
|
|
|
|
blnd_cfg.global_gain = 0xff;
|
|
|
|
|
2017-06-06 04:08:10 +09:00
|
|
|
/* DCN1.0 has output CM before MPC which seems to screw with
|
|
|
|
* pre-multiplied alpha.
|
|
|
|
*/
|
2017-11-07 06:38:55 +09:00
|
|
|
blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
|
2017-07-26 09:51:26 +09:00
|
|
|
pipe_ctx->stream->output_color_space)
|
2017-06-06 04:08:10 +09:00
|
|
|
&& per_pixel_alpha;
|
2017-11-07 06:38:55 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: remove hack
|
|
|
|
* Note: currently there is a bug in init_hw such that
|
|
|
|
* on resume from hibernate, BIOS sets up MPCC0, and
|
|
|
|
* we do mpcc_remove but the mpcc cannot go to idle
|
|
|
|
* after remove. This cause us to pick mpcc1 here,
|
|
|
|
* which causes a pstate hang for yet unknown reason.
|
|
|
|
*/
|
|
|
|
mpcc_id = hubp->inst;
|
|
|
|
|
|
|
|
/* check if this MPCC is already being used */
|
|
|
|
new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
|
|
|
|
/* remove MPCC if being used */
|
|
|
|
if (new_mpcc != NULL)
|
|
|
|
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
|
2017-11-17 04:29:10 +09:00
|
|
|
else
|
|
|
|
if (dc->debug.sanity_checks)
|
|
|
|
mpc->funcs->assert_mpcc_idle_before_connect(
|
|
|
|
dc->res_pool->mpc, mpcc_id);
|
2017-11-07 06:38:55 +09:00
|
|
|
|
|
|
|
/* Call MPC to insert new plane */
|
|
|
|
new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
|
|
|
|
mpc_tree_params,
|
|
|
|
&blnd_cfg,
|
|
|
|
NULL,
|
|
|
|
NULL,
|
|
|
|
hubp->inst,
|
|
|
|
mpcc_id);
|
|
|
|
|
|
|
|
ASSERT(new_mpcc != NULL);
|
|
|
|
|
|
|
|
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
|
|
|
|
hubp->mpcc_id = mpcc_id;
|
2017-11-09 07:24:54 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void update_scaler(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
bool per_pixel_alpha =
|
|
|
|
pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
|
|
|
|
|
|
|
|
/* TODO: proper fix once fpga works */
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 00:51:21 +09:00
|
|
|
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
|
|
|
|
pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
|
2017-05-09 04:19:06 +09:00
|
|
|
/* scaler configuration */
|
2017-10-06 05:47:49 +09:00
|
|
|
pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
|
|
|
|
pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
|
2017-11-09 07:24:54 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void update_dchubp_dpp(
|
|
|
|
struct dc *dc,
|
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct dc_state *context)
|
|
|
|
{
|
|
|
|
struct hubp *hubp = pipe_ctx->plane_res.hubp;
|
|
|
|
struct dpp *dpp = pipe_ctx->plane_res.dpp;
|
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
|
|
|
union plane_size size = plane_state->plane_size;
|
|
|
|
|
|
|
|
/* depends on DML calculation, DPP clock value may change dynamically */
|
2017-11-22 05:59:42 +09:00
|
|
|
if (plane_state->update_flags.bits.full_update) {
|
2017-12-21 07:17:40 +09:00
|
|
|
dpp->funcs->dpp_dppclk_control(
|
|
|
|
dpp,
|
|
|
|
context->bw.dcn.calc_clk.dppclk_div,
|
|
|
|
true);
|
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
dc->current_state->bw.dcn.cur_clk.dppclk_div =
|
|
|
|
context->bw.dcn.calc_clk.dppclk_div;
|
|
|
|
context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
|
|
|
|
* VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
|
|
|
|
* VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
|
|
|
|
*/
|
|
|
|
if (plane_state->update_flags.bits.full_update) {
|
2017-12-19 04:09:19 +09:00
|
|
|
hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
|
2017-10-06 05:47:49 +09:00
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
hubp->funcs->hubp_setup(
|
|
|
|
hubp,
|
|
|
|
&pipe_ctx->dlg_regs,
|
|
|
|
&pipe_ctx->ttu_regs,
|
|
|
|
&pipe_ctx->rq_regs,
|
|
|
|
&pipe_ctx->pipe_dlg_param);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
if (plane_state->update_flags.bits.full_update ||
|
|
|
|
plane_state->update_flags.bits.bpp_change)
|
|
|
|
update_dpp(dpp, plane_state);
|
|
|
|
|
|
|
|
if (plane_state->update_flags.bits.full_update ||
|
|
|
|
plane_state->update_flags.bits.per_pixel_alpha_change)
|
|
|
|
update_mpcc(dc, pipe_ctx);
|
|
|
|
|
|
|
|
if (plane_state->update_flags.bits.full_update ||
|
|
|
|
plane_state->update_flags.bits.per_pixel_alpha_change ||
|
|
|
|
plane_state->update_flags.bits.scaling_change ||
|
|
|
|
plane_state->update_flags.bits.position_change) {
|
|
|
|
update_scaler(pipe_ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (plane_state->update_flags.bits.full_update ||
|
2017-11-22 05:59:42 +09:00
|
|
|
plane_state->update_flags.bits.scaling_change ||
|
|
|
|
plane_state->update_flags.bits.position_change) {
|
2017-11-09 07:24:54 +09:00
|
|
|
hubp->funcs->mem_program_viewport(
|
|
|
|
hubp,
|
|
|
|
&pipe_ctx->plane_res.scl_data.viewport,
|
|
|
|
&pipe_ctx->plane_res.scl_data.viewport_c);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (plane_state->update_flags.bits.full_update) {
|
|
|
|
/*gamut remap*/
|
|
|
|
program_gamut_remap(pipe_ctx);
|
|
|
|
|
|
|
|
program_output_csc(dc,
|
|
|
|
pipe_ctx,
|
|
|
|
pipe_ctx->stream->output_color_space,
|
|
|
|
pipe_ctx->stream->csc_color_matrix.matrix,
|
|
|
|
hubp->opp_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (plane_state->update_flags.bits.full_update ||
|
|
|
|
plane_state->update_flags.bits.horizontal_mirror_change ||
|
|
|
|
plane_state->update_flags.bits.rotation_change ||
|
|
|
|
plane_state->update_flags.bits.swizzle_change ||
|
2017-11-17 07:08:44 +09:00
|
|
|
plane_state->update_flags.bits.dcc_change ||
|
2017-12-08 00:42:33 +09:00
|
|
|
plane_state->update_flags.bits.bpp_change ||
|
|
|
|
plane_state->update_flags.bits.scaling_change) {
|
2017-11-09 07:24:54 +09:00
|
|
|
hubp->funcs->hubp_program_surface_config(
|
|
|
|
hubp,
|
|
|
|
plane_state->format,
|
|
|
|
&plane_state->tiling_info,
|
|
|
|
&size,
|
|
|
|
plane_state->rotation,
|
|
|
|
&plane_state->dcc,
|
|
|
|
plane_state->horizontal_mirror);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-11-07 04:40:31 +09:00
|
|
|
hubp->power_gated = false;
|
|
|
|
|
2017-09-28 23:40:10 +09:00
|
|
|
dc->hwss.update_plane_addr(dc, pipe_ctx);
|
|
|
|
|
2017-07-28 21:16:27 +09:00
|
|
|
if (is_pipe_tree_visible(pipe_ctx))
|
2017-10-03 03:39:42 +09:00
|
|
|
hubp->funcs->set_blank(hubp, false);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-08-05 04:42:36 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void program_all_pipe_in_tree(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-12-05 06:58:11 +09:00
|
|
|
|
2017-06-03 08:00:45 +09:00
|
|
|
if (pipe_ctx->top_pipe == NULL) {
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_global_sync(
|
|
|
|
pipe_ctx->stream_res.tg);
|
2017-12-05 06:58:11 +09:00
|
|
|
|
|
|
|
if (pipe_ctx->stream_res.tg->funcs->set_blank)
|
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank(
|
|
|
|
pipe_ctx->stream_res.tg,
|
|
|
|
!is_pipe_tree_visible(pipe_ctx));
|
2017-06-03 08:00:45 +09:00
|
|
|
}
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state != NULL) {
|
2017-11-09 04:50:06 +09:00
|
|
|
if (pipe_ctx->plane_state->update_flags.bits.full_update)
|
|
|
|
dcn10_enable_plane(dc, pipe_ctx, context);
|
2017-08-05 04:42:36 +09:00
|
|
|
|
2017-11-09 07:24:54 +09:00
|
|
|
update_dchubp_dpp(dc, pipe_ctx, context);
|
2017-10-04 04:03:49 +09:00
|
|
|
|
2017-12-21 00:07:42 +09:00
|
|
|
if (pipe_ctx->plane_state->update_flags.bits.full_update ||
|
|
|
|
pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
|
|
|
|
pipe_ctx->plane_state->update_flags.bits.gamma_change)
|
2017-11-01 05:27:59 +09:00
|
|
|
dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
|
2017-11-04 05:21:37 +09:00
|
|
|
|
2017-11-11 05:40:52 +09:00
|
|
|
/* dcn10_translate_regamma_to_hw_format takes 750us to finish
|
|
|
|
* only do gamma programming for full update.
|
2017-11-04 05:21:37 +09:00
|
|
|
* TODO: This can be further optimized/cleaned up
|
|
|
|
* Always call this for now since it does memcmp inside before
|
|
|
|
* doing heavy calculation and programming
|
|
|
|
*/
|
2017-11-11 05:40:52 +09:00
|
|
|
if (pipe_ctx->plane_state->update_flags.bits.full_update)
|
|
|
|
dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-08-25 06:29:24 +09:00
|
|
|
if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
|
2017-05-09 04:19:06 +09:00
|
|
|
program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_pplib_apply_display_requirements(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
|
|
|
|
|
|
|
|
pp_display_cfg->all_displays_in_sync = false;/*todo*/
|
|
|
|
pp_display_cfg->nb_pstate_switch_disable = false;
|
2017-05-04 00:40:40 +09:00
|
|
|
pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
|
|
|
|
pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
|
|
|
|
pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
|
|
|
|
pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
pp_display_cfg->avail_mclk_switch_time_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
|
2017-05-09 04:19:06 +09:00
|
|
|
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
|
|
|
|
pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
|
|
|
|
pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
dce110_fill_display_configs(context, pp_display_cfg);
|
|
|
|
|
|
|
|
if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
|
|
|
|
struct dm_pp_display_configuration)) != 0)
|
|
|
|
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
|
|
|
|
|
|
|
|
dc->prev_display_config = *pp_display_cfg;
|
|
|
|
}
|
|
|
|
|
2017-09-06 01:20:39 +09:00
|
|
|
static void optimize_shared_resources(struct dc *dc)
|
|
|
|
{
|
|
|
|
if (dc->current_state->stream_count == 0) {
|
|
|
|
/* S0i2 message */
|
|
|
|
dcn10_pplib_apply_display_requirements(dc, dc->current_state);
|
|
|
|
}
|
2017-09-28 00:44:43 +09:00
|
|
|
|
|
|
|
if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
|
|
|
|
dcn_bw_notify_pplib_of_wm_ranges(dc);
|
2017-09-06 01:20:39 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ready_shared_resources(struct dc *dc, struct dc_state *context)
|
|
|
|
{
|
|
|
|
/* S0i2 message */
|
|
|
|
if (dc->current_state->stream_count == 0 &&
|
|
|
|
context->stream_count != 0)
|
|
|
|
dcn10_pplib_apply_display_requirements(dc, context);
|
|
|
|
}
|
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
static struct pipe_ctx *find_top_pipe_for_stream(
|
|
|
|
struct dc *dc,
|
|
|
|
struct dc_state *context,
|
|
|
|
const struct dc_stream_state *stream)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *old_pipe_ctx =
|
|
|
|
&dc->current_state->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (pipe_ctx->stream != stream)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!pipe_ctx->top_pipe)
|
|
|
|
return pipe_ctx;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void dcn10_apply_ctx_for_surface(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-08-03 13:22:25 +09:00
|
|
|
const struct dc_stream_state *stream,
|
|
|
|
int num_planes,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-10-31 06:32:14 +09:00
|
|
|
int i;
|
|
|
|
struct timing_generator *tg;
|
2017-12-05 06:58:11 +09:00
|
|
|
struct output_pixel_processor *opp;
|
2017-10-31 06:32:14 +09:00
|
|
|
bool removed_pipe[4] = { false };
|
2017-11-08 01:01:34 +09:00
|
|
|
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
|
2017-11-14 07:22:17 +09:00
|
|
|
bool program_water_mark = false;
|
2017-10-31 06:32:14 +09:00
|
|
|
|
|
|
|
struct pipe_ctx *top_pipe_to_program =
|
|
|
|
find_top_pipe_for_stream(dc, context, stream);
|
|
|
|
|
|
|
|
if (!top_pipe_to_program)
|
|
|
|
return;
|
|
|
|
|
2017-12-05 06:58:11 +09:00
|
|
|
opp = top_pipe_to_program->stream_res.opp;
|
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
tg = top_pipe_to_program->stream_res.tg;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-12-16 00:26:13 +09:00
|
|
|
dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
|
2017-08-03 13:22:25 +09:00
|
|
|
|
|
|
|
if (num_planes == 0) {
|
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
/* OTG blank before remove all front end */
|
2017-12-05 06:58:11 +09:00
|
|
|
if (tg->funcs->set_blank)
|
|
|
|
tg->funcs->set_blank(tg, true);
|
2017-08-03 13:22:25 +09:00
|
|
|
}
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
/* Disconnect unused mpcc */
|
2017-07-13 07:38:04 +09:00
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
2017-06-15 07:58:04 +09:00
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *old_pipe_ctx =
|
2017-08-26 05:16:10 +09:00
|
|
|
&dc->current_state->res_ctx.pipe_ctx[i];
|
2017-07-19 04:50:47 +09:00
|
|
|
/*
|
|
|
|
* Powergate reused pipes that are not powergated
|
|
|
|
* fairly hacky right now, using opp_id as indicator
|
2017-10-31 06:32:14 +09:00
|
|
|
* TODO: After move dc_post to dc_update, this will
|
|
|
|
* be removed.
|
2017-07-19 04:50:47 +09:00
|
|
|
*/
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
|
2017-10-31 06:32:14 +09:00
|
|
|
if (old_pipe_ctx->stream_res.tg == tg &&
|
|
|
|
old_pipe_ctx->plane_res.hubp &&
|
|
|
|
old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
|
2017-11-07 04:40:31 +09:00
|
|
|
dcn10_disable_plane(dc, pipe_ctx);
|
2017-07-21 05:17:17 +09:00
|
|
|
/*
|
|
|
|
* power down fe will unlock when calling reset, need
|
|
|
|
* to lock it back here. Messy, need rework.
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
|
2017-07-21 05:17:17 +09:00
|
|
|
}
|
2017-07-19 04:50:47 +09:00
|
|
|
}
|
2017-06-15 07:58:04 +09:00
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
if (!pipe_ctx->plane_state &&
|
|
|
|
old_pipe_ctx->plane_state &&
|
|
|
|
old_pipe_ctx->stream_res.tg == tg) {
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
plane_atomic_disconnect(dc, old_pipe_ctx);
|
|
|
|
removed_pipe[i] = true;
|
2017-06-15 07:58:04 +09:00
|
|
|
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Reset mpcc for pipe %d\n",
|
|
|
|
old_pipe_ctx->pipe_idx);
|
|
|
|
}
|
2017-07-13 07:38:04 +09:00
|
|
|
}
|
2017-06-15 07:58:04 +09:00
|
|
|
|
2017-11-22 05:42:17 +09:00
|
|
|
if (num_planes > 0)
|
2017-10-31 06:32:14 +09:00
|
|
|
program_all_pipe_in_tree(dc, top_pipe_to_program, context);
|
|
|
|
|
2017-12-16 00:26:13 +09:00
|
|
|
dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-11-16 06:21:34 +09:00
|
|
|
if (num_planes == 0)
|
|
|
|
false_optc_underflow_wa(dc, stream, tg);
|
|
|
|
|
2017-10-31 06:32:14 +09:00
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct pipe_ctx *old_pipe_ctx =
|
|
|
|
&dc->current_state->res_ctx.pipe_ctx[i];
|
2017-11-14 07:22:17 +09:00
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (pipe_ctx->stream == stream &&
|
|
|
|
pipe_ctx->plane_state &&
|
|
|
|
pipe_ctx->plane_state->update_flags.bits.full_update)
|
|
|
|
program_water_mark = true;
|
2017-10-31 06:32:14 +09:00
|
|
|
|
2017-11-18 00:44:15 +09:00
|
|
|
if (removed_pipe[i])
|
2017-11-07 04:40:31 +09:00
|
|
|
dcn10_disable_plane(dc, old_pipe_ctx);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-11-14 07:22:17 +09:00
|
|
|
if (program_water_mark) {
|
|
|
|
if (dc->debug.sanity_checks) {
|
|
|
|
/* pstate stuck check after watermark update */
|
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
|
|
|
}
|
2017-11-18 00:44:15 +09:00
|
|
|
|
2017-11-14 07:22:17 +09:00
|
|
|
/* watermark is for all pipes */
|
|
|
|
hubbub1_program_watermarks(dc->res_pool->hubbub,
|
|
|
|
&context->bw.dcn.watermarks, ref_clk_mhz);
|
2017-11-08 01:01:34 +09:00
|
|
|
|
2017-11-14 07:22:17 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
|
|
|
/* pstate stuck check after watermark update */
|
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
|
|
|
}
|
2017-11-08 01:01:34 +09:00
|
|
|
}
|
2017-11-09 07:24:54 +09:00
|
|
|
/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
2017-06-08 02:53:30 +09:00
|
|
|
"\n============== Watermark parameters ==============\n"
|
|
|
|
"a.urgent_ns: %d \n"
|
|
|
|
"a.cstate_enter_plus_exit: %d \n"
|
|
|
|
"a.cstate_exit: %d \n"
|
|
|
|
"a.pstate_change: %d \n"
|
|
|
|
"a.pte_meta_urgent: %d \n"
|
|
|
|
"b.urgent_ns: %d \n"
|
|
|
|
"b.cstate_enter_plus_exit: %d \n"
|
|
|
|
"b.cstate_exit: %d \n"
|
|
|
|
"b.pstate_change: %d \n"
|
|
|
|
"b.pte_meta_urgent: %d \n",
|
|
|
|
context->bw.dcn.watermarks.a.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.b.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.b.pte_meta_urgent_ns
|
|
|
|
);
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\nc.urgent_ns: %d \n"
|
|
|
|
"c.cstate_enter_plus_exit: %d \n"
|
|
|
|
"c.cstate_exit: %d \n"
|
|
|
|
"c.pstate_change: %d \n"
|
|
|
|
"c.pte_meta_urgent: %d \n"
|
|
|
|
"d.urgent_ns: %d \n"
|
|
|
|
"d.cstate_enter_plus_exit: %d \n"
|
|
|
|
"d.cstate_exit: %d \n"
|
|
|
|
"d.pstate_change: %d \n"
|
|
|
|
"d.pte_meta_urgent: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
context->bw.dcn.watermarks.c.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.d.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.d.pte_meta_urgent_ns
|
|
|
|
);
|
2017-11-09 07:24:54 +09:00
|
|
|
*/
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_set_bandwidth(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-08-26 05:16:10 +09:00
|
|
|
struct dc_state *context,
|
2017-05-09 04:19:06 +09:00
|
|
|
bool decrease_allowed)
|
|
|
|
{
|
2017-08-21 03:25:19 +09:00
|
|
|
struct pp_smu_display_requirement_rv *smu_req_cur =
|
|
|
|
&dc->res_pool->pp_smu_req;
|
|
|
|
struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
|
|
|
|
struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
|
|
|
return;
|
|
|
|
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
|
2017-08-26 05:16:10 +09:00
|
|
|
> dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
|
2017-05-09 04:19:06 +09:00
|
|
|
dc->res_pool->display_clock->funcs->set_clock(
|
|
|
|
dc->res_pool->display_clock,
|
2017-05-03 06:29:48 +09:00
|
|
|
context->bw.dcn.calc_clk.dispclk_khz);
|
2017-08-26 05:16:10 +09:00
|
|
|
dc->current_state->bw.dcn.cur_clk.dispclk_khz =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.calc_clk.dispclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
|
2017-08-26 05:16:10 +09:00
|
|
|
> dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
|
2017-08-21 03:25:19 +09:00
|
|
|
smu_req.hard_min_dcefclk_khz =
|
|
|
|
context->bw.dcn.calc_clk.dcfclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
|
2017-08-26 05:16:10 +09:00
|
|
|
> dc->current_state->bw.dcn.cur_clk.fclk_khz) {
|
2017-08-21 03:25:19 +09:00
|
|
|
smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
|
2017-05-04 00:40:40 +09:00
|
|
|
}
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
|
2017-08-26 05:16:10 +09:00
|
|
|
> dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
|
|
|
|
dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
|
|
|
|
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
|
|
|
|
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
|
|
|
|
}
|
2017-08-21 03:25:19 +09:00
|
|
|
|
|
|
|
smu_req.display_count = context->stream_count;
|
|
|
|
|
|
|
|
if (pp_smu->set_display_requirement)
|
|
|
|
pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
|
|
|
|
|
|
|
|
*smu_req_cur = smu_req;
|
|
|
|
|
2017-05-04 00:40:40 +09:00
|
|
|
/* Decrease in freq is increase in period so opposite comparison for dram_ccm */
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
|
2017-08-26 05:16:10 +09:00
|
|
|
< dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
|
|
|
|
dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.calc_clk.dram_ccm_us;
|
|
|
|
context->bw.dcn.cur_clk.dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.dram_ccm_us;
|
|
|
|
}
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
|
2017-08-26 05:16:10 +09:00
|
|
|
< dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
|
|
|
|
dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.calc_clk.min_active_dram_ccm_us;
|
|
|
|
context->bw.dcn.cur_clk.min_active_dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.min_active_dram_ccm_us;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
dcn10_pplib_apply_display_requirements(dc, context);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
|
|
|
|
2017-07-15 03:07:16 +09:00
|
|
|
/* need to fix this function. not doing the right thing here */
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_drr(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes, int vmin, int vmax)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
struct drr_params params = {0};
|
|
|
|
|
|
|
|
params.vertical_total_max = vmax;
|
|
|
|
params.vertical_total_min = vmin;
|
|
|
|
|
|
|
|
/* TODO: If multiple pipes are to be supported, you need
|
|
|
|
* some GSL stuff
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_pipes; i++) {
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void get_position(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes,
|
|
|
|
struct crtc_position *position)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
/* TODO: handle pipes > 1
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_pipes; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes, const struct dc_static_screen_events *events)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
unsigned int value = 0;
|
|
|
|
|
|
|
|
if (events->surface_update)
|
|
|
|
value |= 0x80;
|
|
|
|
if (events->cursor_update)
|
|
|
|
value |= 0x2;
|
|
|
|
|
|
|
|
for (i = 0; i < num_pipes; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->
|
|
|
|
set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_plane_config(
|
2017-08-02 04:00:25 +09:00
|
|
|
const struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct resource_context *res_ctx)
|
|
|
|
{
|
|
|
|
/* TODO */
|
|
|
|
program_gamut_remap(pipe_ctx);
|
|
|
|
}
|
|
|
|
|
2017-07-07 04:42:04 +09:00
|
|
|
static void dcn10_config_stereo_parameters(
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
|
2017-06-09 05:55:02 +09:00
|
|
|
{
|
2017-07-26 09:51:26 +09:00
|
|
|
enum view_3d_format view_format = stream->view_format;
|
2017-06-09 05:55:02 +09:00
|
|
|
enum dc_timing_3d_format timing_3d_format =\
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->timing.timing_3d_format;
|
2017-06-09 05:55:02 +09:00
|
|
|
bool non_stereo_timing = false;
|
|
|
|
|
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
|
|
|
|
non_stereo_timing = true;
|
|
|
|
|
|
|
|
if (non_stereo_timing == false &&
|
|
|
|
view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
|
|
|
|
|
|
|
|
flags->PROGRAM_STEREO = 1;
|
|
|
|
flags->PROGRAM_POLARITY = 1;
|
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
|
|
|
|
enum display_dongle_type dongle = \
|
2017-07-23 09:05:20 +09:00
|
|
|
stream->sink->link->ddc->dongle_type;
|
2017-06-09 05:55:02 +09:00
|
|
|
if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
|
|
|
|
dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
|
|
|
|
dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
|
|
|
|
flags->DISABLE_STEREO_DP_SYNC = 1;
|
|
|
|
}
|
|
|
|
flags->RIGHT_EYE_POLARITY =\
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->timing.flags.RIGHT_EYE_3D_POLARITY;
|
2017-06-09 05:55:02 +09:00
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
|
|
|
|
flags->FRAME_PACKED = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
|
2017-06-09 05:55:02 +09:00
|
|
|
{
|
|
|
|
struct crtc_stereo_flags flags = { 0 };
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
2017-06-09 05:55:02 +09:00
|
|
|
|
|
|
|
dcn10_config_stereo_parameters(stream, &flags);
|
|
|
|
|
2017-12-13 04:14:10 +09:00
|
|
|
pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp,
|
2017-06-09 05:55:02 +09:00
|
|
|
flags.PROGRAM_STEREO == 1 ? true:false,
|
2017-12-13 04:14:10 +09:00
|
|
|
&stream->timing);
|
2017-06-09 05:55:02 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_stereo(
|
|
|
|
pipe_ctx->stream_res.tg,
|
2017-07-26 09:51:26 +09:00
|
|
|
&stream->timing,
|
2017-06-09 05:55:02 +09:00
|
|
|
&flags);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-12-20 06:47:02 +09:00
|
|
|
static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < res_pool->pipe_count; i++) {
|
|
|
|
if (res_pool->hubps[i]->inst == mpcc_inst)
|
|
|
|
return res_pool->hubps[i];
|
|
|
|
}
|
|
|
|
ASSERT(false);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2017-07-24 23:47:02 +09:00
|
|
|
static void dcn10_wait_for_mpcc_disconnect(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-07-24 23:47:02 +09:00
|
|
|
struct resource_pool *res_pool,
|
|
|
|
struct pipe_ctx *pipe_ctx)
|
2017-07-24 04:18:57 +09:00
|
|
|
{
|
2017-12-20 06:47:02 +09:00
|
|
|
int mpcc_inst;
|
2017-07-24 04:18:57 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
if (!pipe_ctx->stream_res.opp)
|
2017-07-24 23:47:02 +09:00
|
|
|
return;
|
|
|
|
|
2017-12-20 06:47:02 +09:00
|
|
|
for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
|
|
|
|
if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
|
|
|
|
struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
|
|
|
|
|
|
|
|
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
|
|
|
|
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
|
|
|
|
hubp->funcs->set_blank(hubp, true);
|
2017-07-24 23:47:02 +09:00
|
|
|
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
|
|
|
|
"[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
|
|
|
|
i);*/
|
2017-07-24 04:18:57 +09:00
|
|
|
}
|
|
|
|
}
|
2017-07-24 23:47:02 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-10-25 04:16:38 +09:00
|
|
|
dcn10_verify_allow_pstate_change_high(dc);
|
2017-08-04 03:20:14 +09:00
|
|
|
}
|
|
|
|
|
2017-07-24 04:18:57 +09:00
|
|
|
}
|
|
|
|
|
2017-07-07 04:42:04 +09:00
|
|
|
static bool dcn10_dummy_display_power_gating(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-07-07 04:42:04 +09:00
|
|
|
uint8_t controller_id,
|
|
|
|
struct dc_bios *dcb,
|
2017-07-15 03:07:16 +09:00
|
|
|
enum pipe_gating_control power_gating)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-07-31 02:59:26 +09:00
|
|
|
struct timing_generator *tg = pipe_ctx->stream_res.tg;
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state == NULL)
|
2017-07-15 03:07:16 +09:00
|
|
|
return;
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->status.is_flip_pending =
|
2017-10-03 03:39:42 +09:00
|
|
|
pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
|
|
|
|
pipe_ctx->plane_res.hubp);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-10-03 03:39:42 +09:00
|
|
|
plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
|
|
|
|
if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
|
2017-07-15 03:07:16 +09:00
|
|
|
tg->funcs->is_stereo_left_eye) {
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->status.is_right_eye =
|
2017-07-31 02:59:26 +09:00
|
|
|
!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
|
2017-07-15 03:07:16 +09:00
|
|
|
}
|
|
|
|
}
|
2017-07-07 04:42:04 +09:00
|
|
|
|
2017-10-25 03:13:16 +09:00
|
|
|
void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
|
|
|
|
{
|
2017-10-27 05:30:44 +09:00
|
|
|
if (hws->ctx->dc->res_pool->hubbub != NULL)
|
|
|
|
hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
|
2017-10-25 03:13:16 +09:00
|
|
|
}
|
2017-08-15 07:17:01 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static const struct hw_sequencer_funcs dcn10_funcs = {
|
2017-06-03 06:25:49 +09:00
|
|
|
.program_gamut_remap = program_gamut_remap,
|
2017-06-29 06:21:42 +09:00
|
|
|
.program_csc_matrix = program_csc_matrix,
|
2017-07-08 06:21:45 +09:00
|
|
|
.init_hw = dcn10_init_hw,
|
2017-05-09 04:19:06 +09:00
|
|
|
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
|
|
|
|
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
|
|
|
|
.set_plane_config = set_plane_config,
|
2017-08-03 23:19:58 +09:00
|
|
|
.update_plane_addr = dcn10_update_plane_addr,
|
2017-10-25 03:13:16 +09:00
|
|
|
.update_dchub = dcn10_update_dchub,
|
2017-07-15 03:07:16 +09:00
|
|
|
.update_pending_status = dcn10_update_pending_status,
|
2017-05-09 04:19:06 +09:00
|
|
|
.set_input_transfer_func = dcn10_set_input_transfer_func,
|
|
|
|
.set_output_transfer_func = dcn10_set_output_transfer_func,
|
|
|
|
.power_down = dce110_power_down,
|
|
|
|
.enable_accelerated_mode = dce110_enable_accelerated_mode,
|
|
|
|
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
|
2017-10-18 04:29:22 +09:00
|
|
|
.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
|
2017-05-09 04:19:06 +09:00
|
|
|
.update_info_frame = dce110_update_info_frame,
|
|
|
|
.enable_stream = dce110_enable_stream,
|
|
|
|
.disable_stream = dce110_disable_stream,
|
|
|
|
.unblank_stream = dce110_unblank_stream,
|
2017-07-07 04:42:04 +09:00
|
|
|
.enable_display_power_gating = dcn10_dummy_display_power_gating,
|
2017-11-07 04:40:31 +09:00
|
|
|
.disable_plane = dcn10_disable_plane,
|
2017-05-09 04:19:06 +09:00
|
|
|
.pipe_control_lock = dcn10_pipe_control_lock,
|
|
|
|
.set_bandwidth = dcn10_set_bandwidth,
|
|
|
|
.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
|
|
|
|
.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
|
|
|
|
.set_drr = set_drr,
|
|
|
|
.get_position = get_position,
|
2017-06-09 05:55:02 +09:00
|
|
|
.set_static_screen_control = set_static_screen_control,
|
2017-07-18 05:04:02 +09:00
|
|
|
.setup_stereo = dcn10_setup_stereo,
|
|
|
|
.set_avmute = dce110_set_avmute,
|
2017-07-24 04:18:57 +09:00
|
|
|
.log_hw_state = dcn10_log_hw_state,
|
2017-08-25 06:40:00 +09:00
|
|
|
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
|
|
|
|
.ready_shared_resources = ready_shared_resources,
|
|
|
|
.optimize_shared_resources = optimize_shared_resources,
|
2017-11-01 04:55:15 +09:00
|
|
|
.pplib_apply_display_requirements =
|
|
|
|
dcn10_pplib_apply_display_requirements,
|
2017-09-26 07:03:14 +09:00
|
|
|
.edp_backlight_control = hwss_edp_backlight_control,
|
2017-11-25 06:31:03 +09:00
|
|
|
.edp_power_control = hwss_edp_power_control,
|
|
|
|
.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
|
2017-05-09 04:19:06 +09:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
void dcn10_hw_sequencer_construct(struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
dc->hwss = dcn10_funcs;
|
|
|
|
}
|
|
|
|
|