2017-05-09 04:19:06 +09:00
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "core_types.h"
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#include "resource.h"
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2017-07-08 06:21:45 +09:00
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#include "custom_float.h"
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2017-05-09 04:19:06 +09:00
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#include "dcn10_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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2017-05-17 05:07:30 +09:00
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#include "dce/dce_hwseq.h"
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2017-05-09 04:19:06 +09:00
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#include "abm.h"
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2017-07-26 11:52:45 +09:00
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#include "dcn10/dcn10_mem_input.h"
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2017-07-06 07:03:04 +09:00
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#include "dcn10/dcn10_dpp.h"
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#include "dcn10/dcn10_mpc.h"
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2017-05-09 04:19:06 +09:00
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#include "timing_generator.h"
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#include "opp.h"
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#include "ipp.h"
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2017-07-08 06:21:45 +09:00
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#include "mpc.h"
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2017-05-09 04:19:06 +09:00
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#include "raven1/DCN/dcn_1_0_offset.h"
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#include "raven1/DCN/dcn_1_0_sh_mask.h"
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#include "vega10/soc15ip.h"
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2017-07-05 19:57:49 +09:00
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#include "reg_helper.h"
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2017-05-09 04:19:06 +09:00
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2017-07-05 19:57:49 +09:00
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#define CTX \
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hws->ctx
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#define REG(reg)\
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hws->regs->reg
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2017-05-09 04:19:06 +09:00
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2017-07-05 19:57:49 +09:00
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#undef FN
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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2017-05-09 04:19:06 +09:00
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2017-08-02 04:00:25 +09:00
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static void log_mpc_crc(struct dc *dc)
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2017-08-03 21:59:12 +09:00
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct dce_hwseq *hws = dc->hwseq;
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if (REG(MPC_CRC_RESULT_GB))
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DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
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REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
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if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
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DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
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REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
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}
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2017-08-03 22:22:14 +09:00
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void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
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{
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static const uint32_t ref_clk_mhz = 48;
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static const unsigned int frac = 10;
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uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
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DTN_INFO("%d.%d \t ",
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us_x10 / frac,
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us_x10 % frac);
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}
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#define DTN_INFO_MICRO_SEC(ref_cycle) \
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print_microsec(dc_ctx, ref_cycle)
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2017-08-04 12:21:46 +09:00
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struct dcn_hubbub_wm_set {
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uint32_t wm_set;
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uint32_t data_urgent;
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uint32_t pte_meta_urgent;
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uint32_t sr_enter;
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uint32_t sr_exit;
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uint32_t dram_clk_chanage;
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};
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struct dcn_hubbub_wm {
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struct dcn_hubbub_wm_set sets[4];
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};
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static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,
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struct dcn_hubbub_wm *wm)
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{
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struct dcn_hubbub_wm_set *s;
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s = &wm->sets[0];
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s->wm_set = 0;
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s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
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s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
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s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
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s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
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s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
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s = &wm->sets[1];
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s->wm_set = 1;
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s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
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s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
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s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
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s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
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s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
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s = &wm->sets[2];
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s->wm_set = 2;
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s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
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s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
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s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
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s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
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s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
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s = &wm->sets[3];
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s->wm_set = 3;
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s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
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s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
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s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
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s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
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s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
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}
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2017-08-02 04:00:25 +09:00
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static void dcn10_log_hubbub_state(struct dc *dc)
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2017-08-04 12:21:46 +09:00
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct dcn_hubbub_wm wm;
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int i;
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dcn10_hubbub_wm_read_state(dc->hwseq, &wm);
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DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
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"sr_enter \t sr_exit \t dram_clk_change \n");
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for (i = 0; i < 4; i++) {
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struct dcn_hubbub_wm_set *s;
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s = &wm.sets[i];
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DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
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DTN_INFO_MICRO_SEC(s->data_urgent);
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DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
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DTN_INFO_MICRO_SEC(s->sr_enter);
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DTN_INFO_MICRO_SEC(s->sr_exit);
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DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
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DTN_INFO("\n");
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}
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DTN_INFO("\n");
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}
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2017-08-02 04:00:25 +09:00
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static void dcn10_log_hw_state(struct dc *dc)
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2017-08-03 21:59:12 +09:00
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct resource_pool *pool = dc->res_pool;
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int i;
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DTN_INFO_BEGIN();
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2017-08-04 12:21:46 +09:00
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dcn10_log_hubbub_state(dc);
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2017-08-03 22:22:14 +09:00
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DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
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"rotation \t mirror \t sw_mode \t "
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"dcc_en \t blank_en \t ttu_dis \t underflow \t "
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2017-08-03 21:59:12 +09:00
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"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
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for (i = 0; i < pool->pipe_count; i++) {
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struct mem_input *mi = pool->mis[i];
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struct dcn_hubp_state s;
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dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
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2017-08-03 22:22:14 +09:00
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DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
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"%xh \t %xh \t %xh \t "
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"%d \t %d \t %d \t %xh \t",
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2017-08-03 21:59:12 +09:00
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i,
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s.pixel_format,
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s.inuse_addr_hi,
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s.viewport_width,
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s.viewport_height,
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s.rotation_angle,
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s.h_mirror_en,
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s.sw_mode,
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s.dcc_en,
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s.blank_en,
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s.ttu_disable,
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2017-08-03 22:22:14 +09:00
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s.underflow_status);
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DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
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DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
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DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
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DTN_INFO("\n");
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2017-08-03 21:59:12 +09:00
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}
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DTN_INFO("\n");
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log_mpc_crc(dc);
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DTN_INFO_END();
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}
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2017-07-15 03:07:16 +09:00
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static void verify_allow_pstate_change_high(
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struct dce_hwseq *hws)
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{
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/* pstate latency is ~20us so if we wait over 40us and pstate allow
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* still not asserted, we are probably stuck and going to hang
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*/
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static unsigned int pstate_wait_timeout_us = 40;
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static unsigned int max_sampled_pstate_wait_us; /* data collection */
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static bool forced_pstate_allow; /* help with revert wa */
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2017-08-05 04:30:45 +09:00
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static bool should_log_hw_state; /* prevent hw state log by default */
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2017-07-15 03:07:16 +09:00
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unsigned int debug_index = 0x7;
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unsigned int debug_data;
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unsigned int force_allow_pstate = 0x30;
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unsigned int i;
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if (forced_pstate_allow) {
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/* we hacked to force pstate allow to prevent hang last time
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* we verify_allow_pstate_change_high. so disable force
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* here so we can check status
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*/
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REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, 0);
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forced_pstate_allow = false;
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}
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/* description "3-0: Pipe0 cursor0 QOS
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* 7-4: Pipe1 cursor0 QOS
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* 11-8: Pipe2 cursor0 QOS
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* 15-12: Pipe3 cursor0 QOS
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* 16: Pipe0 Plane0 Allow Pstate Change
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* 17: Pipe1 Plane0 Allow Pstate Change
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* 18: Pipe2 Plane0 Allow Pstate Change
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* 19: Pipe3 Plane0 Allow Pstate Change
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* 20: Pipe0 Plane1 Allow Pstate Change
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* 21: Pipe1 Plane1 Allow Pstate Change
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* 22: Pipe2 Plane1 Allow Pstate Change
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* 23: Pipe3 Plane1 Allow Pstate Change
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* 24: Pipe0 cursor0 Allow Pstate Change
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* 25: Pipe1 cursor0 Allow Pstate Change
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* 26: Pipe2 cursor0 Allow Pstate Change
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* 27: Pipe3 cursor0 Allow Pstate Change
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* 28: WB0 Allow Pstate Change
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* 29: WB1 Allow Pstate Change
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* 30: Arbiter's allow_pstate_change
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* 31: SOC pstate change request
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*/
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REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
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for (i = 0; i < pstate_wait_timeout_us; i++) {
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debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
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if (debug_data & (1 << 30))
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return;
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if (max_sampled_pstate_wait_us < i)
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max_sampled_pstate_wait_us = i;
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udelay(1);
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}
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/* force pstate allow to prevent system hang
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* and break to debugger to investigate
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*/
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REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
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forced_pstate_allow = true;
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2017-08-03 21:59:12 +09:00
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2017-08-05 04:30:45 +09:00
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if (should_log_hw_state) {
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2017-08-02 04:00:25 +09:00
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dcn10_log_hw_state(hws->ctx->dc);
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2017-08-05 04:30:45 +09:00
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}
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2017-08-03 21:59:12 +09:00
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2017-07-15 03:07:16 +09:00
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BREAK_TO_DEBUGGER();
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}
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2017-05-09 04:19:06 +09:00
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static void enable_dppclk(
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2017-07-05 19:57:49 +09:00
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struct dce_hwseq *hws,
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2017-05-09 04:19:06 +09:00
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uint8_t plane_id,
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uint32_t requested_pix_clk,
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bool dppclk_div)
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{
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2017-07-05 19:57:49 +09:00
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dm_logger_write(hws->ctx->logger, LOG_SURFACE,
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2017-05-09 04:19:06 +09:00
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"dppclk_rate_control for pipe %d programed to %d\n",
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plane_id,
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dppclk_div);
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2017-07-08 00:24:13 +09:00
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if (hws->shifts->DPPCLK_RATE_CONTROL)
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2017-07-05 19:57:49 +09:00
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REG_UPDATE_2(DPP_CONTROL[plane_id],
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2017-07-08 00:24:13 +09:00
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|
DPPCLK_RATE_CONTROL, dppclk_div,
|
2017-05-09 04:19:06 +09:00
|
|
|
DPP_CLOCK_ENABLE, 1);
|
2017-07-08 00:24:13 +09:00
|
|
|
else
|
|
|
|
REG_UPDATE(DPP_CONTROL[plane_id],
|
2017-05-09 04:19:06 +09:00
|
|
|
DPP_CLOCK_ENABLE, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_power_gating_plane(
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws,
|
2017-05-09 04:19:06 +09:00
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
bool force_on = 1; /* disable power gating */
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
force_on = 0;
|
|
|
|
|
|
|
|
/* DCHUBP0/1/2/3 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* DPP0/1/2/3 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
|
|
|
|
REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-07-13 11:35:52 +09:00
|
|
|
static void disable_vga(
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
REG_WRITE(D1VGA_CONTROL, 0);
|
|
|
|
REG_WRITE(D2VGA_CONTROL, 0);
|
|
|
|
REG_WRITE(D3VGA_CONTROL, 0);
|
|
|
|
REG_WRITE(D4VGA_CONTROL, 0);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void dpp_pg_control(
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws,
|
2017-05-09 04:19:06 +09:00
|
|
|
unsigned int dpp_inst,
|
|
|
|
bool power_on)
|
|
|
|
{
|
|
|
|
uint32_t power_gate = power_on ? 0 : 1;
|
|
|
|
uint32_t pwr_status = power_on ? 0 : 2;
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
if (hws->ctx->dc->debug.disable_dpp_power_gate)
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
|
|
|
|
switch (dpp_inst) {
|
|
|
|
case 0: /* DPP0 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN1_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN1_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN1_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 1: /* DPP1 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN3_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN3_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN3_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 2: /* DPP2 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN5_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN5_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN5_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 3: /* DPP3 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN7_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN7_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN7_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-24 07:30:15 +09:00
|
|
|
static uint32_t convert_and_clamp(
|
|
|
|
uint32_t wm_ns,
|
|
|
|
uint32_t refclk_mhz,
|
|
|
|
uint32_t clamp_value)
|
|
|
|
{
|
|
|
|
uint32_t ret_val = 0;
|
|
|
|
ret_val = wm_ns * refclk_mhz;
|
|
|
|
ret_val /= 1000;
|
|
|
|
|
|
|
|
if (ret_val > clamp_value)
|
|
|
|
ret_val = clamp_value;
|
|
|
|
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void program_watermarks(
|
|
|
|
struct dce_hwseq *hws,
|
|
|
|
struct dcn_watermark_set *watermarks,
|
|
|
|
unsigned int refclk_mhz)
|
|
|
|
{
|
|
|
|
uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
|
|
|
|
/*
|
|
|
|
* Need to clamp to max of the register values (i.e. no wrap)
|
|
|
|
* for dcn1, all wm registers are 21-bit wide
|
|
|
|
*/
|
|
|
|
uint32_t prog_wm_value;
|
|
|
|
|
2017-08-04 04:46:10 +09:00
|
|
|
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
|
|
|
|
|
2017-07-24 07:30:15 +09:00
|
|
|
/* Repeat for water mark set A, B, C and D. */
|
|
|
|
/* clock state A */
|
|
|
|
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
|
|
|
|
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"URGENCY_WATERMARK_A calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->a.urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->a.pte_meta_urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->a.cstate_pstate.cstate_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_EXIT_WATERMARK_A calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->a.cstate_pstate.pstate_change_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n\n",
|
|
|
|
watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
/* clock state B */
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"URGENCY_WATERMARK_B calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->b.urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->b.pte_meta_urgent_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->b.pte_meta_urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_ENTER_WATERMARK_B calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->b.cstate_pstate.cstate_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_EXIT_WATERMARK_B calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->b.cstate_pstate.pstate_change_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
|
|
|
|
|
|
|
|
/* clock state C */
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"URGENCY_WATERMARK_C calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->c.urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->c.pte_meta_urgent_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->c.pte_meta_urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_ENTER_WATERMARK_C calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->c.cstate_pstate.cstate_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_EXIT_WATERMARK_C calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->c.cstate_pstate.pstate_change_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
|
|
|
|
|
|
|
|
/* clock state D */
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"URGENCY_WATERMARK_D calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->d.urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->d.pte_meta_urgent_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->d.pte_meta_urgent_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_ENTER_WATERMARK_D calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->d.cstate_pstate.cstate_exit_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"SR_EXIT_WATERMARK_D calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n",
|
|
|
|
watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
|
|
|
|
|
|
|
|
|
|
|
prog_wm_value = convert_and_clamp(
|
|
|
|
watermarks->d.cstate_pstate.pstate_change_ns,
|
|
|
|
refclk_mhz, 0x1fffff);
|
|
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
|
|
|
|
dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
|
|
|
|
"DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
|
|
|
|
"HW register value = 0x%x\n\n",
|
|
|
|
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
|
2017-08-04 04:46:10 +09:00
|
|
|
|
2017-07-24 07:30:15 +09:00
|
|
|
REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
|
|
|
|
DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
|
|
|
|
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
|
|
|
|
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
|
|
|
|
|
|
|
|
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
|
|
|
|
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
|
|
|
|
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void dcn10_update_dchub(
|
|
|
|
struct dce_hwseq *hws,
|
|
|
|
struct dchub_init_data *dh_data)
|
|
|
|
{
|
|
|
|
/* TODO: port code from dal2 */
|
|
|
|
switch (dh_data->fb_mode) {
|
|
|
|
case FRAME_BUFFER_MODE_ZFB_ONLY:
|
|
|
|
/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
|
|
|
|
SDPIF_FB_TOP, 0);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
|
|
|
|
SDPIF_FB_BASE, 0x0FFFF);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
|
|
|
|
SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
|
|
|
|
SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
|
|
|
|
SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
|
|
|
|
dh_data->zfb_size_in_byte - 1) >> 22);
|
|
|
|
break;
|
|
|
|
case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
|
|
|
|
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
|
|
|
|
SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
|
|
|
|
SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
|
|
|
|
SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
|
|
|
|
dh_data->zfb_size_in_byte - 1) >> 22);
|
|
|
|
break;
|
|
|
|
case FRAME_BUFFER_MODE_LOCAL_ONLY:
|
|
|
|
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
|
|
|
|
SDPIF_AGP_BASE, 0);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
|
|
|
|
SDPIF_AGP_BOT, 0X03FFFF);
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
|
|
|
|
SDPIF_AGP_TOP, 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dh_data->dchub_initialzied = true;
|
|
|
|
dh_data->dchub_info_valid = false;
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void hubp_pg_control(
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws,
|
2017-05-09 04:19:06 +09:00
|
|
|
unsigned int hubp_inst,
|
|
|
|
bool power_on)
|
|
|
|
{
|
|
|
|
uint32_t power_gate = power_on ? 0 : 1;
|
|
|
|
uint32_t pwr_status = power_on ? 0 : 2;
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
if (hws->ctx->dc->debug.disable_hubp_power_gate)
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
|
|
|
|
switch (hubp_inst) {
|
|
|
|
case 0: /* DCHUBP0 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN0_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN0_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN0_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 1: /* DCHUBP1 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN2_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN2_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN2_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 2: /* DCHUBP2 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN4_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN4_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN4_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
case 3: /* DCHUBP3 */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DOMAIN6_PG_CONFIG,
|
2017-05-09 04:19:06 +09:00
|
|
|
DOMAIN6_POWER_GATE, power_gate);
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WAIT(DOMAIN6_PG_STATUS,
|
2017-08-04 10:23:04 +09:00
|
|
|
DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
|
|
|
|
1, 1000);
|
2017-05-09 04:19:06 +09:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void power_on_plane(
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws,
|
2017-06-15 07:58:04 +09:00
|
|
|
int plane_id)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
2017-05-09 04:19:06 +09:00
|
|
|
IP_REQUEST_EN, 1);
|
2017-07-05 19:57:49 +09:00
|
|
|
dpp_pg_control(hws, plane_id, true);
|
|
|
|
hubp_pg_control(hws, plane_id, true);
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
2017-05-09 04:19:06 +09:00
|
|
|
IP_REQUEST_EN, 0);
|
2017-07-05 19:57:49 +09:00
|
|
|
dm_logger_write(hws->ctx->logger, LOG_DC,
|
2017-06-15 07:58:04 +09:00
|
|
|
"Un-gated front end for pipe %d\n", plane_id);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void bios_golden_init(struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
struct dc_bios *bp = dc->ctx->dc_bios;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* initialize dcn global */
|
|
|
|
bp->funcs->enable_disp_power_gating(bp,
|
|
|
|
CONTROLLER_ID_D0, ASIC_PIPE_INIT);
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
/* initialize dcn per pipe */
|
|
|
|
bp->funcs->enable_disp_power_gating(bp,
|
|
|
|
CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_init_hw(struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
int i;
|
2017-07-08 06:21:45 +09:00
|
|
|
struct abm *abm = dc->res_pool->abm;
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
2017-07-08 06:21:45 +09:00
|
|
|
REG_WRITE(REFCLK_CNTL, 0);
|
|
|
|
REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (!dc->debug.disable_clock_gate) {
|
2017-07-05 19:57:49 +09:00
|
|
|
/* enable all DCN clock gating */
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
|
|
|
|
|
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
enable_power_gating_plane(dc->hwseq, true);
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* end of FPGA. Below if real ASIC */
|
|
|
|
|
|
|
|
bios_golden_init(dc);
|
|
|
|
|
2017-07-13 11:35:52 +09:00
|
|
|
disable_vga(dc->hwseq);
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = 0; i < dc->link_count; i++) {
|
|
|
|
/* Power up AND update implementation according to the
|
|
|
|
* required signal (which may be different from the
|
|
|
|
* default signal on connector).
|
|
|
|
*/
|
2017-07-23 09:05:20 +09:00
|
|
|
struct dc_link *link = dc->links[i];
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
link->link_enc->funcs->hw_init(link->link_enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
2017-07-08 06:21:45 +09:00
|
|
|
struct transform *xfm = dc->res_pool->transforms[i];
|
|
|
|
struct timing_generator *tg = dc->res_pool->timing_generators[i];
|
2017-06-02 07:35:54 +09:00
|
|
|
|
2017-07-08 06:21:45 +09:00
|
|
|
xfm->funcs->transform_reset(xfm);
|
2017-07-22 06:46:50 +09:00
|
|
|
dc->res_pool->mpc->funcs->remove(
|
|
|
|
dc->res_pool->mpc, dc->res_pool->opps[i], i);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* Blank controller using driver code instead of
|
|
|
|
* command table.
|
|
|
|
*/
|
|
|
|
tg->funcs->set_blank(tg, true);
|
|
|
|
hwss_wait_for_blank_complete(tg);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->audio_count; i++) {
|
|
|
|
struct audio *audio = dc->res_pool->audios[i];
|
|
|
|
|
|
|
|
audio->funcs->hw_init(audio);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (abm != NULL) {
|
|
|
|
abm->funcs->init_backlight(abm);
|
|
|
|
abm->funcs->abm_init(abm);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (!dc->debug.disable_clock_gate) {
|
2017-05-31 04:26:14 +09:00
|
|
|
/* enable all DCN clock gating */
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
|
2017-05-31 04:26:14 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
|
2017-05-31 04:26:14 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
|
|
|
|
}
|
2017-05-31 04:26:14 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
enable_power_gating_plane(dc->hwseq, true);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static enum dc_status dcn10_prog_pixclk_crtc_otg(
|
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct validate_context *context,
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
2017-05-09 04:19:06 +09:00
|
|
|
enum dc_color_space color_space;
|
|
|
|
struct tg_color black_color = {0};
|
2017-07-26 09:51:26 +09:00
|
|
|
bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
|
2017-05-09 04:19:06 +09:00
|
|
|
false:true;
|
2017-07-26 09:51:26 +09:00
|
|
|
bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
|
|
|
|
/* by upper caller loop, pipe0 is parent pipe and be called first.
|
|
|
|
* back end is set up by for pipe0. Other children pipe share back end
|
|
|
|
* with pipe 0. No program is needed.
|
|
|
|
*/
|
|
|
|
if (pipe_ctx->top_pipe != NULL)
|
|
|
|
return DC_OK;
|
|
|
|
|
|
|
|
/* TODO check if timing_changed, disable stream if timing changed */
|
|
|
|
|
|
|
|
/* HW program guide assume display already disable
|
|
|
|
* by unplug sequence. OTG assume stop.
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
|
|
|
|
pipe_ctx->clock_source,
|
2017-07-31 04:17:43 +09:00
|
|
|
&pipe_ctx->stream_res.pix_clk_params,
|
2017-05-09 04:19:06 +09:00
|
|
|
&pipe_ctx->pll_settings)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
}
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_timing(
|
|
|
|
pipe_ctx->stream_res.tg,
|
2017-07-26 09:51:26 +09:00
|
|
|
&stream->timing,
|
2017-05-09 04:19:06 +09:00
|
|
|
true);
|
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
|
|
|
|
pipe_ctx->stream_res.opp,
|
2017-05-09 04:19:06 +09:00
|
|
|
enableStereo,
|
|
|
|
rightEyePolarity);
|
|
|
|
|
|
|
|
#if 0 /* move to after enable_crtc */
|
|
|
|
/* TODO: OPP FMT, ABM. etc. should be done here. */
|
|
|
|
/* or FPGA now. instance 0 only. TODO: move to opp.c */
|
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
|
|
|
|
pipe_ctx->stream_res.opp,
|
2017-05-09 04:19:06 +09:00
|
|
|
&stream->bit_depth_params,
|
|
|
|
&stream->clamping);
|
|
|
|
#endif
|
|
|
|
/* program otg blank color */
|
2017-07-26 09:51:26 +09:00
|
|
|
color_space = stream->output_color_space;
|
2017-05-09 04:19:06 +09:00
|
|
|
color_space_to_black_color(dc, color_space, &black_color);
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank_color(
|
|
|
|
pipe_ctx->stream_res.tg,
|
2017-05-09 04:19:06 +09:00
|
|
|
&black_color);
|
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
|
|
|
|
hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* VTG is within DCHUB command block. DCFCLK is always on */
|
2017-07-31 02:59:26 +09:00
|
|
|
if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
|
2017-05-09 04:19:06 +09:00
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO program crtc source select for non-virtual signal*/
|
|
|
|
/* TODO program FMT */
|
|
|
|
/* TODO setup link_enc */
|
|
|
|
/* TODO set stream attributes */
|
|
|
|
/* TODO program audio */
|
|
|
|
/* TODO enable stream if timing changed */
|
|
|
|
/* TODO unblank stream if DP */
|
|
|
|
|
|
|
|
return DC_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void reset_back_end_for_pipe(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct validate_context *context)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-07-31 03:36:12 +09:00
|
|
|
if (pipe_ctx->stream_res.stream_enc == NULL) {
|
2017-05-09 04:19:06 +09:00
|
|
|
pipe_ctx->stream = NULL;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODOFPGA break core_link_disable_stream into 2 functions:
|
|
|
|
* disable_stream and disable_link. disable_link will disable PHYPLL
|
|
|
|
* which is used by otg. Move disable_link after disable_crtc
|
|
|
|
*/
|
|
|
|
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
|
|
|
core_link_disable_stream(pipe_ctx);
|
|
|
|
|
|
|
|
/* by upper caller loop, parent pipe: pipe0, will be reset last.
|
|
|
|
* back end share by all pipes and will be disable only when disable
|
|
|
|
* parent pipe.
|
|
|
|
*/
|
|
|
|
if (pipe_ctx->top_pipe == NULL) {
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
|
|
|
resource_unreference_clock_source(
|
|
|
|
&context->res_ctx, dc->res_pool,
|
|
|
|
&pipe_ctx->clock_source);
|
|
|
|
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++)
|
|
|
|
if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (i == dc->res_pool->pipe_count)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pipe_ctx->stream = NULL;
|
2017-06-15 07:58:04 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Reset back end for pipe %d, tg:%d\n",
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-07-24 04:22:47 +09:00
|
|
|
/* trigger HW to start disconnect plane from stream on the next vsync */
|
2017-08-02 04:00:25 +09:00
|
|
|
static void plane_atomic_disconnect(struct dc *dc,
|
2017-06-15 07:58:04 +09:00
|
|
|
int fe_idx)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-06-15 07:58:04 +09:00
|
|
|
struct mem_input *mi = dc->res_pool->mis[fe_idx];
|
2017-07-22 06:46:50 +09:00
|
|
|
struct mpc *mpc = dc->res_pool->mpc;
|
|
|
|
int opp_id, z_idx;
|
|
|
|
int mpcc_id = -1;
|
|
|
|
|
|
|
|
/* look at tree rather than mi here to know if we already reset */
|
|
|
|
for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
|
|
|
|
struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-07-22 06:46:50 +09:00
|
|
|
for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) {
|
|
|
|
if (opp->mpc_tree.dpp[z_idx] == fe_idx) {
|
|
|
|
mpcc_id = opp->mpc_tree.mpcc[z_idx];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (mpcc_id != -1)
|
|
|
|
break;
|
|
|
|
}
|
2017-07-24 04:22:47 +09:00
|
|
|
/*Already reset*/
|
2017-07-22 06:46:50 +09:00
|
|
|
if (opp_id == dc->res_pool->pipe_count)
|
2017-07-24 04:22:47 +09:00
|
|
|
return;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-24 23:47:02 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-07-12 22:02:54 +09:00
|
|
|
mi->funcs->dcc_control(mi, false, false);
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-24 23:47:02 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
|
2017-07-22 06:46:50 +09:00
|
|
|
mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx);
|
2017-07-15 02:42:23 +09:00
|
|
|
}
|
|
|
|
|
2017-07-24 04:22:47 +09:00
|
|
|
/* disable HW used by plane.
|
|
|
|
* note: cannot disable until disconnect is complete */
|
2017-08-02 04:00:25 +09:00
|
|
|
static void plane_atomic_disable(struct dc *dc,
|
2017-07-15 02:42:23 +09:00
|
|
|
int fe_idx)
|
|
|
|
{
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
|
|
|
struct mem_input *mi = dc->res_pool->mis[fe_idx];
|
2017-07-22 06:46:50 +09:00
|
|
|
struct mpc *mpc = dc->res_pool->mpc;
|
2017-07-29 03:16:13 +09:00
|
|
|
int opp_id = mi->opp_id;
|
2017-07-15 02:42:23 +09:00
|
|
|
|
2017-07-29 03:16:13 +09:00
|
|
|
if (opp_id == 0xf)
|
2017-07-15 02:42:23 +09:00
|
|
|
return;
|
|
|
|
|
2017-07-22 06:46:50 +09:00
|
|
|
mpc->funcs->wait_for_idle(mpc, mi->mpcc_id);
|
|
|
|
dc->res_pool->opps[mi->opp_id]->mpcc_disconnect_pending[mi->mpcc_id] = false;
|
2017-07-24 23:47:02 +09:00
|
|
|
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
|
|
|
|
"[debug_mpo: atomic disable finished on mpcc %d]\n",
|
|
|
|
fe_idx);*/
|
2017-07-12 22:02:54 +09:00
|
|
|
|
2017-07-15 02:42:23 +09:00
|
|
|
mi->funcs->set_blank(mi, true);
|
2017-07-22 06:46:50 +09:00
|
|
|
/*todo: unhack this*/
|
|
|
|
mi->opp_id = 0xf;
|
|
|
|
mi->mpcc_id = 0xf;
|
2017-07-15 02:42:23 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
|
2017-07-13 00:54:10 +09:00
|
|
|
REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
|
|
|
|
HUBP_CLOCK_ENABLE, 0);
|
|
|
|
REG_UPDATE(DPP_CONTROL[fe_idx],
|
|
|
|
DPP_CLOCK_ENABLE, 0);
|
2017-07-13 07:38:04 +09:00
|
|
|
|
2017-07-29 03:16:13 +09:00
|
|
|
if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
|
|
|
|
REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
|
2017-07-13 07:38:04 +09:00
|
|
|
OPP_PIPE_CLOCK_EN, 0);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-06-15 07:58:04 +09:00
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-24 23:47:02 +09:00
|
|
|
/*
|
|
|
|
* kill power to plane hw
|
2017-07-24 04:22:47 +09:00
|
|
|
* note: cannot power down until plane is disable
|
2017-07-24 23:47:02 +09:00
|
|
|
*/
|
2017-08-02 04:00:25 +09:00
|
|
|
static void plane_atomic_power_down(struct dc *dc, int fe_idx)
|
2017-07-24 04:22:47 +09:00
|
|
|
{
|
2017-07-24 23:47:02 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-07-22 06:46:50 +09:00
|
|
|
struct transform *xfm = dc->res_pool->transforms[fe_idx];
|
2017-07-24 23:47:02 +09:00
|
|
|
|
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 1);
|
|
|
|
dpp_pg_control(hws, fe_idx, false);
|
|
|
|
hubp_pg_control(hws, fe_idx, false);
|
2017-07-22 06:46:50 +09:00
|
|
|
xfm->funcs->transform_reset(xfm);
|
2017-07-24 23:47:02 +09:00
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
|
|
|
IP_REQUEST_EN, 0);
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Power gated front end %d\n", fe_idx);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-24 23:47:02 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-07-24 04:22:47 +09:00
|
|
|
}
|
2017-07-24 23:47:02 +09:00
|
|
|
|
2017-07-24 04:22:47 +09:00
|
|
|
|
|
|
|
static void reset_front_end(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-07-24 04:22:47 +09:00
|
|
|
int fe_idx)
|
|
|
|
{
|
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-07-22 06:46:50 +09:00
|
|
|
struct timing_generator *tg;
|
|
|
|
int opp_id = dc->res_pool->mis[fe_idx]->opp_id;
|
2017-07-24 04:22:47 +09:00
|
|
|
|
|
|
|
/*Already reset*/
|
|
|
|
if (opp_id == 0xf)
|
|
|
|
return;
|
|
|
|
|
2017-07-22 06:46:50 +09:00
|
|
|
tg = dc->res_pool->timing_generators[opp_id];
|
2017-07-24 04:22:47 +09:00
|
|
|
tg->funcs->lock(tg);
|
|
|
|
|
|
|
|
plane_atomic_disconnect(dc, fe_idx);
|
|
|
|
|
|
|
|
REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
|
|
|
|
tg->funcs->unlock(tg);
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-22 06:46:50 +09:00
|
|
|
verify_allow_pstate_change_high(hws);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
|
|
|
if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
|
|
|
|
REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
|
2017-08-04 10:23:04 +09:00
|
|
|
VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
|
|
|
|
1, 100000);
|
2017-07-24 04:22:47 +09:00
|
|
|
|
|
|
|
plane_atomic_disable(dc, fe_idx);
|
|
|
|
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Reset front end %d\n",
|
|
|
|
fe_idx);
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
|
2017-06-15 07:58:04 +09:00
|
|
|
{
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-07-22 06:46:50 +09:00
|
|
|
struct transform *xfm = dc->res_pool->transforms[fe_idx];
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
reset_front_end(dc, fe_idx);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
2017-06-15 07:58:04 +09:00
|
|
|
IP_REQUEST_EN, 1);
|
2017-07-05 19:57:49 +09:00
|
|
|
dpp_pg_control(hws, fe_idx, false);
|
|
|
|
hubp_pg_control(hws, fe_idx, false);
|
2017-07-22 06:46:50 +09:00
|
|
|
xfm->funcs->transform_reset(xfm);
|
2017-07-05 19:57:49 +09:00
|
|
|
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
2017-06-15 07:58:04 +09:00
|
|
|
IP_REQUEST_EN, 0);
|
2017-05-09 04:19:06 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
2017-06-15 07:58:04 +09:00
|
|
|
"Power gated front end %d\n", fe_idx);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
static void reset_hw_ctx_wrap(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-06-15 07:58:04 +09:00
|
|
|
struct validate_context *context)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
/* Reset Front End*/
|
2017-07-24 23:47:02 +09:00
|
|
|
/* Lock*/
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
|
2017-07-31 02:59:26 +09:00
|
|
|
struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
|
2017-07-24 23:47:02 +09:00
|
|
|
|
|
|
|
if (cur_pipe_ctx->stream)
|
|
|
|
tg->funcs->lock(tg);
|
|
|
|
}
|
|
|
|
/* Disconnect*/
|
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
|
|
|
struct pipe_ctx *pipe_ctx_old =
|
|
|
|
&dc->current_context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (!pipe_ctx->stream ||
|
2017-07-27 22:55:38 +09:00
|
|
|
!pipe_ctx->plane_state ||
|
2017-07-24 23:47:02 +09:00
|
|
|
pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
|
|
|
|
|
|
|
|
plane_atomic_disconnect(dc, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Unlock*/
|
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
|
|
|
|
struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
|
2017-07-31 02:59:26 +09:00
|
|
|
struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
|
2017-07-24 23:47:02 +09:00
|
|
|
|
|
|
|
if (cur_pipe_ctx->stream)
|
|
|
|
tg->funcs->unlock(tg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable and Powerdown*/
|
2017-06-15 07:58:04 +09:00
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
|
|
|
struct pipe_ctx *pipe_ctx_old =
|
|
|
|
&dc->current_context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
/*if (!pipe_ctx_old->stream)
|
|
|
|
continue;*/
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->stream && pipe_ctx->plane_state
|
2017-07-24 23:47:02 +09:00
|
|
|
&& !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
plane_atomic_disable(dc, i);
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (!pipe_ctx->stream || !pipe_ctx->plane_state)
|
2017-07-24 23:47:02 +09:00
|
|
|
plane_atomic_power_down(dc, i);
|
2017-06-15 07:58:04 +09:00
|
|
|
}
|
2017-07-24 23:47:02 +09:00
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
/* Reset Back End*/
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
|
|
|
struct pipe_ctx *pipe_ctx_old =
|
|
|
|
&dc->current_context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
|
|
|
if (!pipe_ctx_old->stream)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!pipe_ctx->stream ||
|
|
|
|
pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
|
2017-06-15 07:58:04 +09:00
|
|
|
reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
static bool patch_address_for_sbs_tb_stereo(
|
|
|
|
struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-05-09 04:19:06 +09:00
|
|
|
bool sec_split = pipe_ctx->top_pipe &&
|
2017-07-27 22:55:38 +09:00
|
|
|
pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
|
|
|
|
if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
|
2017-07-26 09:51:26 +09:00
|
|
|
(pipe_ctx->stream->timing.timing_3d_format ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TIMING_3D_FORMAT_SIDE_BY_SIDE ||
|
2017-07-26 09:51:26 +09:00
|
|
|
pipe_ctx->stream->timing.timing_3d_format ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
|
2017-07-27 22:55:38 +09:00
|
|
|
*addr = plane_state->address.grph_stereo.left_addr;
|
|
|
|
plane_state->address.grph_stereo.left_addr =
|
|
|
|
plane_state->address.grph_stereo.right_addr;
|
2017-05-09 04:19:06 +09:00
|
|
|
return true;
|
2017-06-29 03:36:25 +09:00
|
|
|
} else {
|
2017-07-26 09:51:26 +09:00
|
|
|
if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
|
|
|
|
plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
|
|
|
|
plane_state->address.grph_stereo.right_addr =
|
|
|
|
plane_state->address.grph_stereo.left_addr;
|
2017-06-29 03:36:25 +09:00
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-08-05 04:42:36 +09:00
|
|
|
static void toggle_watermark_change_req(struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
uint32_t watermark_change_req;
|
|
|
|
|
|
|
|
REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
|
|
|
|
|
|
|
|
if (watermark_change_req)
|
|
|
|
watermark_change_req = 0;
|
|
|
|
else
|
|
|
|
watermark_change_req = 1;
|
|
|
|
|
|
|
|
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
|
|
|
|
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
bool addr_patched = false;
|
|
|
|
PHYSICAL_ADDRESS_LOC addr;
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state == NULL)
|
2017-05-09 04:19:06 +09:00
|
|
|
return;
|
|
|
|
addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
|
|
|
|
pipe_ctx->plane_res.mi,
|
2017-07-27 22:55:38 +09:00
|
|
|
&plane_state->address,
|
|
|
|
plane_state->flip_immediate);
|
|
|
|
plane_state->status.requested_address = plane_state->address;
|
2017-05-09 04:19:06 +09:00
|
|
|
if (addr_patched)
|
2017-07-27 22:55:38 +09:00
|
|
|
pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool dcn10_set_input_transfer_func(
|
2017-07-27 22:55:38 +09:00
|
|
|
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-31 00:55:55 +09:00
|
|
|
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
|
2017-07-11 03:04:21 +09:00
|
|
|
const struct dc_transfer_func *tf = NULL;
|
2017-05-09 04:19:06 +09:00
|
|
|
bool result = true;
|
|
|
|
|
|
|
|
if (ipp == NULL)
|
|
|
|
return false;
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state->in_transfer_func)
|
|
|
|
tf = plane_state->in_transfer_func;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state->gamma_correction && dce_use_lut(plane_state))
|
2017-06-15 07:58:04 +09:00
|
|
|
ipp->funcs->ipp_program_input_lut(ipp,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->gamma_correction);
|
2017-05-17 05:07:30 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (tf == NULL)
|
|
|
|
ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
|
2017-07-11 03:04:21 +09:00
|
|
|
else if (tf->type == TF_TYPE_PREDEFINED) {
|
|
|
|
switch (tf->tf) {
|
2017-05-09 04:19:06 +09:00
|
|
|
case TRANSFER_FUNCTION_SRGB:
|
|
|
|
ipp->funcs->ipp_set_degamma(ipp,
|
|
|
|
IPP_DEGAMMA_MODE_HW_sRGB);
|
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_BT709:
|
|
|
|
ipp->funcs->ipp_set_degamma(ipp,
|
|
|
|
IPP_DEGAMMA_MODE_HW_xvYCC);
|
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_LINEAR:
|
|
|
|
ipp->funcs->ipp_set_degamma(ipp,
|
|
|
|
IPP_DEGAMMA_MODE_BYPASS);
|
|
|
|
break;
|
|
|
|
case TRANSFER_FUNCTION_PQ:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
2017-07-11 03:04:21 +09:00
|
|
|
} else if (tf->type == TF_TYPE_BYPASS) {
|
2017-05-09 04:19:06 +09:00
|
|
|
ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
|
|
|
|
} else {
|
|
|
|
/*TF_TYPE_DISTRIBUTED_POINTS*/
|
|
|
|
result = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
/*modify the method to handle rgb for arr_points*/
|
|
|
|
static bool convert_to_custom_float(
|
|
|
|
struct pwl_result_data *rgb_resulted,
|
|
|
|
struct curve_points *arr_points,
|
|
|
|
uint32_t hw_points_num)
|
|
|
|
{
|
|
|
|
struct custom_float_format fmt;
|
|
|
|
|
|
|
|
struct pwl_result_data *rgb = rgb_resulted;
|
|
|
|
|
|
|
|
uint32_t i = 0;
|
|
|
|
|
|
|
|
fmt.exponenta_bits = 6;
|
|
|
|
fmt.mantissa_bits = 12;
|
|
|
|
fmt.sign = false;
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[0].x,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[0].custom_float_x)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[0].offset,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[0].custom_float_offset)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[0].slope,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[0].custom_float_slope)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
fmt.mantissa_bits = 10;
|
|
|
|
fmt.sign = false;
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[1].x,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[1].custom_float_x)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[1].y,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[1].custom_float_y)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
arr_points[1].slope,
|
|
|
|
&fmt,
|
|
|
|
&arr_points[1].custom_float_slope)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
fmt.mantissa_bits = 12;
|
|
|
|
fmt.sign = true;
|
|
|
|
|
|
|
|
while (i != hw_points_num) {
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->red,
|
|
|
|
&fmt,
|
|
|
|
&rgb->red_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->green,
|
|
|
|
&fmt,
|
|
|
|
&rgb->green_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->blue,
|
|
|
|
&fmt,
|
|
|
|
&rgb->blue_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->delta_red,
|
|
|
|
&fmt,
|
|
|
|
&rgb->delta_red_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->delta_green,
|
|
|
|
&fmt,
|
|
|
|
&rgb->delta_green_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!convert_to_custom_float_format(
|
|
|
|
rgb->delta_blue,
|
|
|
|
&fmt,
|
|
|
|
&rgb->delta_blue_reg)) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
++rgb;
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#define MAX_REGIONS_NUMBER 34
|
|
|
|
#define MAX_LOW_POINT 25
|
|
|
|
#define NUMBER_SEGMENTS 32
|
|
|
|
|
|
|
|
static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
|
|
|
|
*output_tf, struct pwl_params *regamma_params)
|
|
|
|
{
|
|
|
|
struct curve_points *arr_points;
|
|
|
|
struct pwl_result_data *rgb_resulted;
|
|
|
|
struct pwl_result_data *rgb;
|
|
|
|
struct pwl_result_data *rgb_plus_1;
|
|
|
|
struct fixed31_32 y_r;
|
|
|
|
struct fixed31_32 y_g;
|
|
|
|
struct fixed31_32 y_b;
|
|
|
|
struct fixed31_32 y1_min;
|
|
|
|
struct fixed31_32 y3_max;
|
|
|
|
|
|
|
|
int32_t segment_start, segment_end;
|
|
|
|
int32_t i;
|
|
|
|
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
|
|
|
|
|
|
|
|
if (output_tf == NULL || regamma_params == NULL ||
|
|
|
|
output_tf->type == TF_TYPE_BYPASS)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
arr_points = regamma_params->arr_points;
|
|
|
|
rgb_resulted = regamma_params->rgb_resulted;
|
|
|
|
hw_points = 0;
|
|
|
|
|
|
|
|
memset(regamma_params, 0, sizeof(struct pwl_params));
|
|
|
|
memset(seg_distr, 0, sizeof(seg_distr));
|
|
|
|
|
|
|
|
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
|
|
|
|
/* 32 segments
|
|
|
|
* segments are from 2^-25 to 2^7
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 32 ; i++)
|
|
|
|
seg_distr[i] = 3;
|
|
|
|
|
|
|
|
segment_start = -25;
|
|
|
|
segment_end = 7;
|
|
|
|
} else {
|
|
|
|
/* 10 segments
|
|
|
|
* segment is from 2^-10 to 2^0
|
|
|
|
* There are less than 256 points, for optimization
|
|
|
|
*/
|
|
|
|
seg_distr[0] = 3;
|
|
|
|
seg_distr[1] = 4;
|
|
|
|
seg_distr[2] = 4;
|
|
|
|
seg_distr[3] = 4;
|
|
|
|
seg_distr[4] = 4;
|
|
|
|
seg_distr[5] = 4;
|
|
|
|
seg_distr[6] = 4;
|
|
|
|
seg_distr[7] = 4;
|
|
|
|
seg_distr[8] = 5;
|
|
|
|
seg_distr[9] = 5;
|
|
|
|
|
|
|
|
segment_start = -10;
|
|
|
|
segment_end = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
|
|
|
|
seg_distr[i] = -1;
|
|
|
|
|
|
|
|
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
|
|
|
|
if (seg_distr[k] != -1)
|
|
|
|
hw_points += (1 << seg_distr[k]);
|
|
|
|
}
|
|
|
|
|
|
|
|
j = 0;
|
|
|
|
for (k = 0; k < (segment_end - segment_start); k++) {
|
|
|
|
increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
|
|
|
|
start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
|
|
|
|
for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
|
|
|
|
if (j == hw_points - 1)
|
|
|
|
break;
|
|
|
|
rgb_resulted[j].red = output_tf->tf_pts.red[i];
|
|
|
|
rgb_resulted[j].green = output_tf->tf_pts.green[i];
|
|
|
|
rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
|
|
|
|
j++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* last point */
|
|
|
|
start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
|
|
|
|
rgb_resulted[hw_points - 1].red =
|
|
|
|
output_tf->tf_pts.red[start_index];
|
|
|
|
rgb_resulted[hw_points - 1].green =
|
|
|
|
output_tf->tf_pts.green[start_index];
|
|
|
|
rgb_resulted[hw_points - 1].blue =
|
|
|
|
output_tf->tf_pts.blue[start_index];
|
|
|
|
|
|
|
|
arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
|
|
|
|
dal_fixed31_32_from_int(segment_start));
|
|
|
|
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
|
|
|
|
dal_fixed31_32_from_int(segment_end));
|
|
|
|
arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
|
|
|
|
dal_fixed31_32_from_int(segment_end));
|
|
|
|
|
|
|
|
y_r = rgb_resulted[0].red;
|
|
|
|
y_g = rgb_resulted[0].green;
|
|
|
|
y_b = rgb_resulted[0].blue;
|
|
|
|
|
|
|
|
y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
|
|
|
|
|
|
|
|
arr_points[0].y = y1_min;
|
|
|
|
arr_points[0].slope = dal_fixed31_32_div(
|
|
|
|
arr_points[0].y,
|
|
|
|
arr_points[0].x);
|
|
|
|
y_r = rgb_resulted[hw_points - 1].red;
|
|
|
|
y_g = rgb_resulted[hw_points - 1].green;
|
|
|
|
y_b = rgb_resulted[hw_points - 1].blue;
|
|
|
|
|
|
|
|
/* see comment above, m_arrPoints[1].y should be the Y value for the
|
|
|
|
* region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
|
|
|
|
*/
|
|
|
|
y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
|
|
|
|
|
|
|
|
arr_points[1].y = y3_max;
|
|
|
|
arr_points[2].y = y3_max;
|
|
|
|
|
|
|
|
arr_points[1].slope = dal_fixed31_32_zero;
|
|
|
|
arr_points[2].slope = dal_fixed31_32_zero;
|
|
|
|
|
|
|
|
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
|
|
|
|
/* for PQ, we want to have a straight line from last HW X point,
|
|
|
|
* and the slope to be such that we hit 1.0 at 10000 nits.
|
|
|
|
*/
|
|
|
|
const struct fixed31_32 end_value =
|
|
|
|
dal_fixed31_32_from_int(125);
|
|
|
|
|
|
|
|
arr_points[1].slope = dal_fixed31_32_div(
|
|
|
|
dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
|
|
|
|
dal_fixed31_32_sub(end_value, arr_points[1].x));
|
|
|
|
arr_points[2].slope = dal_fixed31_32_div(
|
|
|
|
dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
|
|
|
|
dal_fixed31_32_sub(end_value, arr_points[1].x));
|
|
|
|
}
|
|
|
|
|
|
|
|
regamma_params->hw_points_num = hw_points;
|
|
|
|
|
|
|
|
i = 1;
|
|
|
|
for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
|
|
|
|
if (seg_distr[k] != -1) {
|
|
|
|
regamma_params->arr_curve_points[k].segments_num =
|
|
|
|
seg_distr[k];
|
|
|
|
regamma_params->arr_curve_points[i].offset =
|
|
|
|
regamma_params->arr_curve_points[k].
|
|
|
|
offset + (1 << seg_distr[k]);
|
|
|
|
}
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (seg_distr[k] != -1)
|
|
|
|
regamma_params->arr_curve_points[k].segments_num =
|
|
|
|
seg_distr[k];
|
|
|
|
|
|
|
|
rgb = rgb_resulted;
|
|
|
|
rgb_plus_1 = rgb_resulted + 1;
|
|
|
|
|
|
|
|
i = 1;
|
|
|
|
|
|
|
|
while (i != hw_points + 1) {
|
|
|
|
if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
|
|
|
|
rgb_plus_1->red = rgb->red;
|
|
|
|
if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
|
|
|
|
rgb_plus_1->green = rgb->green;
|
|
|
|
if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
|
|
|
|
rgb_plus_1->blue = rgb->blue;
|
|
|
|
|
|
|
|
rgb->delta_red = dal_fixed31_32_sub(
|
|
|
|
rgb_plus_1->red,
|
|
|
|
rgb->red);
|
|
|
|
rgb->delta_green = dal_fixed31_32_sub(
|
|
|
|
rgb_plus_1->green,
|
|
|
|
rgb->green);
|
|
|
|
rgb->delta_blue = dal_fixed31_32_sub(
|
|
|
|
rgb_plus_1->blue,
|
|
|
|
rgb->blue);
|
|
|
|
|
|
|
|
++rgb_plus_1;
|
|
|
|
++rgb;
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
convert_to_custom_float(rgb_resulted, arr_points, hw_points);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool dcn10_set_output_transfer_func(
|
|
|
|
struct pipe_ctx *pipe_ctx,
|
2017-07-27 22:33:33 +09:00
|
|
|
const struct dc_stream_state *stream)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
2017-07-31 00:55:55 +09:00
|
|
|
struct transform *xfm = pipe_ctx->plane_res.xfm;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-24 01:13:37 +09:00
|
|
|
if (xfm == NULL)
|
2017-05-10 03:45:54 +09:00
|
|
|
return false;
|
|
|
|
|
2017-07-24 01:13:37 +09:00
|
|
|
xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-26 09:51:26 +09:00
|
|
|
if (stream->out_transfer_func &&
|
|
|
|
stream->out_transfer_func->type ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TF_TYPE_PREDEFINED &&
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->out_transfer_func->tf ==
|
2017-05-09 04:19:06 +09:00
|
|
|
TRANSFER_FUNCTION_SRGB) {
|
2017-07-24 01:13:37 +09:00
|
|
|
xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
|
2017-05-09 04:19:06 +09:00
|
|
|
} else if (dcn10_translate_regamma_to_hw_format(
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->out_transfer_func, &xfm->regamma_params)) {
|
2017-07-24 01:13:37 +09:00
|
|
|
xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
|
|
|
|
xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
|
2017-05-09 04:19:06 +09:00
|
|
|
} else {
|
2017-07-24 01:13:37 +09:00
|
|
|
xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_pipe_control_lock(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe,
|
|
|
|
bool lock)
|
|
|
|
{
|
2017-07-27 18:30:52 +09:00
|
|
|
struct mem_input *mi = NULL;
|
|
|
|
mi = dc->res_pool->mis[pipe->pipe_idx];
|
2017-05-09 04:19:06 +09:00
|
|
|
/* use TG master update lock to lock everything on the TG
|
|
|
|
* therefore only top pipe need to lock
|
|
|
|
*/
|
|
|
|
if (pipe->top_pipe)
|
|
|
|
return;
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (lock)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
else
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool wait_for_reset_trigger_to_occur(
|
|
|
|
struct dc_context *dc_ctx,
|
|
|
|
struct timing_generator *tg)
|
|
|
|
{
|
|
|
|
bool rc = false;
|
|
|
|
|
|
|
|
/* To avoid endless loop we wait at most
|
|
|
|
* frames_to_wait_on_triggered_reset frames for the reset to occur. */
|
|
|
|
const uint32_t frames_to_wait_on_triggered_reset = 10;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
|
|
|
|
|
|
|
|
if (!tg->funcs->is_counter_moving(tg)) {
|
|
|
|
DC_ERROR("TG counter is not moving!\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tg->funcs->did_triggered_reset_occur(tg)) {
|
|
|
|
rc = true;
|
|
|
|
/* usually occurs at i=1 */
|
|
|
|
DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
|
|
|
|
i);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait for one frame. */
|
|
|
|
tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
|
|
|
|
tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (false == rc)
|
|
|
|
DC_ERROR("GSL: Timeout on reset trigger!\n");
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_enable_timing_synchronization(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
int group_index,
|
|
|
|
int group_size,
|
|
|
|
struct pipe_ctx *grouped_pipes[])
|
|
|
|
{
|
|
|
|
struct dc_context *dc_ctx = dc->ctx;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Setting up OTG reset trigger\n");
|
|
|
|
|
|
|
|
for (i = 1; i < group_size; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
|
|
|
|
grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
|
|
|
|
DC_SYNC_INFO("Waiting for trigger\n");
|
|
|
|
|
|
|
|
/* Need to get only check 1 pipe for having reset as all the others are
|
|
|
|
* synchronized. Look at last pipe programmed to reset.
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = 1; i < group_size; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
|
|
|
|
grouped_pipes[i]->stream_res.tg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
DC_SYNC_INFO("Sync complete\n");
|
|
|
|
}
|
|
|
|
|
2017-06-08 02:53:30 +09:00
|
|
|
static void print_rq_dlg_ttu(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *core_dc,
|
2017-06-08 02:53:30 +09:00
|
|
|
struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML TTU Output parameters [%d] ==============\n"
|
|
|
|
"qos_level_low_wm: %d, \n"
|
|
|
|
"qos_level_high_wm: %d, \n"
|
|
|
|
"min_ttu_vblank: %d, \n"
|
|
|
|
"qos_level_flip: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_l: %d, \n"
|
|
|
|
"qos_level_fixed_l: %d, \n"
|
|
|
|
"qos_ramp_disable_l: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_pre_l: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_c: %d, \n"
|
|
|
|
"qos_level_fixed_c: %d, \n"
|
|
|
|
"qos_ramp_disable_c: %d, \n"
|
|
|
|
"refcyc_per_req_delivery_pre_c: %d\n"
|
|
|
|
"=============================================================\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_low_wm,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_high_wm,
|
|
|
|
pipe_ctx->ttu_regs.min_ttu_vblank,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_flip,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_fixed_l,
|
|
|
|
pipe_ctx->ttu_regs.qos_ramp_disable_l,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
|
|
|
|
pipe_ctx->ttu_regs.qos_level_fixed_c,
|
|
|
|
pipe_ctx->ttu_regs.qos_ramp_disable_c,
|
|
|
|
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML DLG Output parameters [%d] ==============\n"
|
|
|
|
"refcyc_h_blank_end: %d, \n"
|
|
|
|
"dlg_vblank_end: %d, \n"
|
|
|
|
"min_dst_y_next_start: %d, \n"
|
|
|
|
"refcyc_per_htotal: %d, \n"
|
|
|
|
"refcyc_x_after_scaler: %d, \n"
|
|
|
|
"dst_y_after_scaler: %d, \n"
|
|
|
|
"dst_y_prefetch: %d, \n"
|
|
|
|
"dst_y_per_vm_vblank: %d, \n"
|
|
|
|
"dst_y_per_row_vblank: %d, \n"
|
|
|
|
"ref_freq_to_pix_freq: %d, \n"
|
|
|
|
"vratio_prefetch: %d, \n"
|
|
|
|
"refcyc_per_pte_group_vblank_l: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_vblank_l: %d, \n"
|
|
|
|
"dst_y_per_pte_row_nom_l: %d, \n"
|
|
|
|
"refcyc_per_pte_group_nom_l: %d, \n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_h_blank_end,
|
|
|
|
pipe_ctx->dlg_regs.dlg_vblank_end,
|
|
|
|
pipe_ctx->dlg_regs.min_dst_y_next_start,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_htotal,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_x_after_scaler,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_after_scaler,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_prefetch,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_row_vblank,
|
|
|
|
pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
|
|
|
|
pipe_ctx->dlg_regs.vratio_prefetch,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\ndst_y_per_meta_row_nom_l: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_nom_l: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_pre_l: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_l: %d, \n"
|
|
|
|
"vratio_prefetch_c: %d, \n"
|
|
|
|
"refcyc_per_pte_group_vblank_c: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_vblank_c: %d, \n"
|
|
|
|
"dst_y_per_pte_row_nom_c: %d, \n"
|
|
|
|
"refcyc_per_pte_group_nom_c: %d, \n"
|
|
|
|
"dst_y_per_meta_row_nom_c: %d, \n"
|
|
|
|
"refcyc_per_meta_chunk_nom_c: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_pre_c: %d, \n"
|
|
|
|
"refcyc_per_line_delivery_c: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
|
|
|
|
pipe_ctx->dlg_regs.vratio_prefetch_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
|
|
|
|
pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
|
|
|
|
);
|
|
|
|
|
|
|
|
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== DML RQ Output parameters [%d] ==============\n"
|
|
|
|
"chunk_size: %d \n"
|
|
|
|
"min_chunk_size: %d \n"
|
|
|
|
"meta_chunk_size: %d \n"
|
|
|
|
"min_meta_chunk_size: %d \n"
|
|
|
|
"dpte_group_size: %d \n"
|
|
|
|
"mpte_group_size: %d \n"
|
|
|
|
"swath_height: %d \n"
|
|
|
|
"pte_row_height_linear: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.swath_height,
|
|
|
|
pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void dcn10_power_on_fe(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct validate_context *context)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
power_on_plane(dc->hwseq,
|
2017-06-15 07:58:04 +09:00
|
|
|
pipe_ctx->pipe_idx);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-06-08 02:53:30 +09:00
|
|
|
/* enable DCFCLK current DCHUB */
|
2017-07-13 00:54:10 +09:00
|
|
|
REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
|
|
|
|
HUBP_CLOCK_ENABLE, 1);
|
|
|
|
|
|
|
|
/* make sure OPP_PIPE_CLOCK_EN = 1 */
|
2017-07-31 02:59:26 +09:00
|
|
|
REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
|
2017-07-13 00:54:10 +09:00
|
|
|
OPP_PIPE_CLOCK_EN, 1);
|
2017-07-22 06:35:16 +09:00
|
|
|
/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
|
2017-06-08 02:53:30 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state) {
|
2017-06-08 02:53:30 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Pipe:%d 0x%x: addr hi:0x%x, "
|
|
|
|
"addr low:0x%x, "
|
|
|
|
"src: %d, %d, %d,"
|
|
|
|
" %d; dst: %d, %d, %d, %d;\n",
|
2017-05-09 04:19:06 +09:00
|
|
|
pipe_ctx->pipe_idx,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state,
|
|
|
|
plane_state->address.grph.addr.high_part,
|
|
|
|
plane_state->address.grph.addr.low_part,
|
|
|
|
plane_state->src_rect.x,
|
|
|
|
plane_state->src_rect.y,
|
|
|
|
plane_state->src_rect.width,
|
|
|
|
plane_state->src_rect.height,
|
|
|
|
plane_state->dst_rect.x,
|
|
|
|
plane_state->dst_rect.y,
|
|
|
|
plane_state->dst_rect.width,
|
|
|
|
plane_state->dst_rect.height);
|
2017-06-08 02:53:30 +09:00
|
|
|
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
|
|
|
|
"Pipe %d: width, height, x, y\n"
|
|
|
|
"viewport:%d, %d, %d, %d\n"
|
|
|
|
"recout: %d, %d, %d, %d\n",
|
|
|
|
pipe_ctx->pipe_idx,
|
2017-07-31 00:51:21 +09:00
|
|
|
pipe_ctx->plane_res.scl_data.viewport.width,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.height,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.x,
|
|
|
|
pipe_ctx->plane_res.scl_data.viewport.y,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.width,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.height,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.x,
|
|
|
|
pipe_ctx->plane_res.scl_data.recout.y);
|
2017-06-08 02:53:30 +09:00
|
|
|
print_rq_dlg_ttu(dc, pipe_ctx);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-08-04 03:20:14 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
|
|
|
struct xfm_grph_csc_adjustment adjust;
|
|
|
|
memset(&adjust, 0, sizeof(adjust));
|
|
|
|
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
|
|
|
|
|
|
|
|
|
2017-07-26 09:51:26 +09:00
|
|
|
if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
|
|
|
|
adjust.temperature_matrix[0] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[0];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[1] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[1];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[2] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[2];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[3] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[4];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[4] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[5];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[5] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[6];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[6] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[8];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[7] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[9];
|
2017-05-09 04:19:06 +09:00
|
|
|
adjust.temperature_matrix[8] =
|
|
|
|
pipe_ctx->stream->
|
2017-07-26 09:51:26 +09:00
|
|
|
gamut_remap_matrix.matrix[10];
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-06-29 06:21:42 +09:00
|
|
|
|
|
|
|
static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
|
|
|
|
enum dc_color_space colorspace,
|
|
|
|
uint16_t *matrix)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct out_csc_color_matrix tbl_entry;
|
|
|
|
|
2017-07-26 09:51:26 +09:00
|
|
|
if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
|
2017-06-29 06:21:42 +09:00
|
|
|
== true) {
|
|
|
|
enum dc_color_space color_space =
|
2017-07-26 09:51:26 +09:00
|
|
|
pipe_ctx->stream->output_color_space;
|
2017-06-29 06:21:42 +09:00
|
|
|
|
|
|
|
//uint16_t matrix[12];
|
|
|
|
for (i = 0; i < 12; i++)
|
2017-07-26 09:51:26 +09:00
|
|
|
tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
|
2017-06-29 06:21:42 +09:00
|
|
|
|
|
|
|
tbl_entry.color_space = color_space;
|
|
|
|
//tbl_entry.regval = matrix;
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
|
2017-06-29 06:21:42 +09:00
|
|
|
}
|
|
|
|
}
|
2017-05-12 06:15:14 +09:00
|
|
|
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state->visible)
|
2017-05-12 06:15:14 +09:00
|
|
|
return true;
|
|
|
|
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
|
|
|
|
return true;
|
|
|
|
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-06-06 04:08:10 +09:00
|
|
|
static bool is_rgb_cspace(enum dc_color_space output_color_space)
|
|
|
|
{
|
|
|
|
switch (output_color_space) {
|
|
|
|
case COLOR_SPACE_SRGB:
|
|
|
|
case COLOR_SPACE_SRGB_LIMITED:
|
|
|
|
case COLOR_SPACE_2020_RGB_FULLRANGE:
|
|
|
|
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
|
|
|
|
case COLOR_SPACE_ADOBERGB:
|
|
|
|
return true;
|
|
|
|
case COLOR_SPACE_YCBCR601:
|
|
|
|
case COLOR_SPACE_YCBCR709:
|
|
|
|
case COLOR_SPACE_YCBCR601_LIMITED:
|
|
|
|
case COLOR_SPACE_YCBCR709_LIMITED:
|
|
|
|
case COLOR_SPACE_2020_YCBCR:
|
|
|
|
return false;
|
|
|
|
default:
|
|
|
|
/* Add a case to switch */
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-07 03:27:49 +09:00
|
|
|
static void dcn10_get_surface_visual_confirm_color(
|
|
|
|
const struct pipe_ctx *pipe_ctx,
|
|
|
|
struct tg_color *color)
|
|
|
|
{
|
|
|
|
uint32_t color_value = MAX_TG_COLOR_VALUE;
|
|
|
|
|
2017-07-31 00:51:21 +09:00
|
|
|
switch (pipe_ctx->plane_res.scl_data.format) {
|
2017-07-07 03:27:49 +09:00
|
|
|
case PIXEL_FORMAT_ARGB8888:
|
|
|
|
/* set boarder color to red */
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PIXEL_FORMAT_ARGB2101010:
|
|
|
|
/* set boarder color to blue */
|
|
|
|
color->color_b_cb = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_420BPP8:
|
|
|
|
/* set boarder color to green */
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_420BPP10:
|
|
|
|
/* set boarder color to yellow */
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
break;
|
|
|
|
case PIXEL_FORMAT_FP16:
|
|
|
|
/* set boarder color to white */
|
|
|
|
color->color_r_cr = color_value;
|
|
|
|
color->color_b_cb = color_value;
|
|
|
|
color->color_g_y = color_value;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-15 07:17:01 +09:00
|
|
|
static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
|
|
|
|
struct vm_system_aperture_param *apt,
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
PHYSICAL_ADDRESS_LOC physical_page_number;
|
|
|
|
uint32_t logical_addr_low;
|
|
|
|
uint32_t logical_addr_high;
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
|
|
|
|
PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
|
|
|
|
PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
|
|
|
LOGICAL_ADDR, &logical_addr_low);
|
|
|
|
|
|
|
|
REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
|
|
|
LOGICAL_ADDR, &logical_addr_high);
|
|
|
|
|
|
|
|
apt->sys_default.quad_part = physical_page_number.quad_part << 12;
|
|
|
|
apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
|
|
|
|
apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Temporary read settings, future will get values from kmd directly */
|
|
|
|
static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi,
|
|
|
|
struct vm_context0_param *vm0,
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
PHYSICAL_ADDRESS_LOC fb_base;
|
|
|
|
PHYSICAL_ADDRESS_LOC fb_offset;
|
|
|
|
uint32_t fb_base_value;
|
|
|
|
uint32_t fb_offset_value;
|
|
|
|
|
|
|
|
REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
|
|
|
|
REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
|
|
|
|
PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
|
|
|
PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
|
|
|
|
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
|
|
|
|
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
|
|
|
|
LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
|
|
|
|
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
|
|
|
|
LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
|
|
|
|
|
|
|
|
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
|
|
|
|
PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
|
|
|
|
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
|
|
|
|
PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
|
|
|
|
* Therefore we need to do
|
|
|
|
* DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
|
|
|
|
* - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
|
|
|
|
*/
|
|
|
|
fb_base.quad_part = (uint64_t)fb_base_value << 24;
|
|
|
|
fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
|
|
|
|
vm0->pte_base.quad_part += fb_base.quad_part;
|
|
|
|
vm0->pte_base.quad_part -= fb_offset.quad_part;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_program_pte_vm(struct mem_input *mem_input,
|
|
|
|
enum surface_pixel_format format,
|
|
|
|
union dc_tiling_info *tiling_info,
|
|
|
|
enum dc_rotation_angle rotation,
|
|
|
|
struct dce_hwseq *hws)
|
|
|
|
{
|
|
|
|
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
|
|
|
|
struct vm_system_aperture_param apt = { {{ 0 } } };
|
|
|
|
struct vm_context0_param vm0 = { { { 0 } } };
|
|
|
|
|
|
|
|
|
|
|
|
mmhub_read_vm_system_aperture_settings(mi, &apt, hws);
|
|
|
|
mmhub_read_vm_context0_settings(mi, &vm0, hws);
|
|
|
|
|
|
|
|
mem_input->funcs->mem_input_set_vm_system_aperture_settings(mem_input, &apt);
|
|
|
|
mem_input->funcs->mem_input_set_vm_context0_settings(mem_input, &vm0);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void update_dchubp_dpp(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct validate_context *context)
|
|
|
|
{
|
2017-07-05 19:57:49 +09:00
|
|
|
struct dce_hwseq *hws = dc->hwseq;
|
2017-07-31 00:55:55 +09:00
|
|
|
struct mem_input *mi = pipe_ctx->plane_res.mi;
|
|
|
|
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
|
|
|
union plane_size size = plane_state->plane_size;
|
2017-05-09 04:19:06 +09:00
|
|
|
struct default_adjustment ocsc = {0};
|
2017-07-22 06:46:50 +09:00
|
|
|
struct mpcc_cfg mpcc_cfg = {0};
|
|
|
|
struct pipe_ctx *top_pipe;
|
2017-07-27 22:55:38 +09:00
|
|
|
bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-06-03 08:01:37 +09:00
|
|
|
/* TODO: proper fix once fpga works */
|
2017-05-09 04:19:06 +09:00
|
|
|
/* depends on DML calculation, DPP clock value may change dynamically */
|
|
|
|
enable_dppclk(
|
2017-07-05 19:57:49 +09:00
|
|
|
dc->hwseq,
|
2017-05-09 04:19:06 +09:00
|
|
|
pipe_ctx->pipe_idx,
|
2017-07-31 04:17:43 +09:00
|
|
|
pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
|
2017-05-03 06:29:48 +09:00
|
|
|
context->bw.dcn.calc_clk.dppclk_div);
|
2017-05-04 00:40:40 +09:00
|
|
|
dc->current_context->bw.dcn.cur_clk.dppclk_div =
|
|
|
|
context->bw.dcn.calc_clk.dppclk_div;
|
|
|
|
context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-05 19:57:49 +09:00
|
|
|
/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
|
|
|
|
* VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
|
|
|
|
* VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-03 23:19:58 +09:00
|
|
|
dc->hwss.update_plane_addr(dc, pipe_ctx);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
mi->funcs->mem_input_setup(
|
|
|
|
mi,
|
|
|
|
&pipe_ctx->dlg_regs,
|
|
|
|
&pipe_ctx->ttu_regs,
|
|
|
|
&pipe_ctx->rq_regs,
|
|
|
|
&pipe_ctx->pipe_dlg_param);
|
|
|
|
|
2017-07-31 00:51:21 +09:00
|
|
|
size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->config.gpu_vm_support)
|
2017-08-15 07:17:01 +09:00
|
|
|
dcn10_program_pte_vm(
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.mi,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->format,
|
|
|
|
&plane_state->tiling_info,
|
2017-08-15 07:17:01 +09:00
|
|
|
plane_state->rotation,
|
|
|
|
hws
|
|
|
|
);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
ipp->funcs->ipp_setup(ipp,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->format,
|
2017-05-09 04:19:06 +09:00
|
|
|
1,
|
|
|
|
IPP_OUTPUT_FORMAT_12_BIT_FIX);
|
|
|
|
|
2017-07-22 06:46:50 +09:00
|
|
|
mpcc_cfg.mi = mi;
|
2017-07-31 02:55:28 +09:00
|
|
|
mpcc_cfg.opp = pipe_ctx->stream_res.opp;
|
2017-07-22 06:46:50 +09:00
|
|
|
for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
|
|
|
|
mpcc_cfg.z_index++;
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.surface_visual_confirm)
|
2017-07-22 06:46:50 +09:00
|
|
|
dcn10_get_surface_visual_confirm_color(
|
|
|
|
pipe_ctx, &mpcc_cfg.black_color);
|
2017-06-02 07:35:54 +09:00
|
|
|
else
|
2017-07-22 06:46:50 +09:00
|
|
|
color_space_to_black_color(
|
|
|
|
dc, pipe_ctx->stream->output_color_space,
|
|
|
|
&mpcc_cfg.black_color);
|
2017-06-02 07:35:54 +09:00
|
|
|
mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
|
2017-06-06 04:08:10 +09:00
|
|
|
/* DCN1.0 has output CM before MPC which seems to screw with
|
|
|
|
* pre-multiplied alpha.
|
|
|
|
*/
|
|
|
|
mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
|
2017-07-26 09:51:26 +09:00
|
|
|
pipe_ctx->stream->output_color_space)
|
2017-06-06 04:08:10 +09:00
|
|
|
&& per_pixel_alpha;
|
2017-07-22 06:46:50 +09:00
|
|
|
dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-07-31 00:51:21 +09:00
|
|
|
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
|
|
|
|
pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
|
2017-05-09 04:19:06 +09:00
|
|
|
/* scaler configuration */
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(
|
|
|
|
pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data);
|
2017-07-14 05:42:58 +09:00
|
|
|
mi->funcs->mem_program_viewport(mi,
|
2017-07-31 00:51:21 +09:00
|
|
|
&pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/*gamut remap*/
|
|
|
|
program_gamut_remap(pipe_ctx);
|
|
|
|
|
|
|
|
/*TODO add adjustments parameters*/
|
2017-07-26 09:51:26 +09:00
|
|
|
ocsc.out_color_space = pipe_ctx->stream->output_color_space;
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(pipe_ctx->plane_res.xfm, &ocsc);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
mi->funcs->mem_input_program_surface_config(
|
|
|
|
mi,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->format,
|
|
|
|
&plane_state->tiling_info,
|
2017-05-09 04:19:06 +09:00
|
|
|
&size,
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->rotation,
|
|
|
|
&plane_state->dcc,
|
|
|
|
plane_state->horizontal_mirror);
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-05-12 06:15:14 +09:00
|
|
|
mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
2017-08-05 04:42:36 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static void program_all_pipe_in_tree(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct validate_context *context)
|
|
|
|
{
|
|
|
|
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
|
|
|
|
|
2017-06-03 08:00:45 +09:00
|
|
|
if (pipe_ctx->top_pipe == NULL) {
|
2017-05-09 04:19:06 +09:00
|
|
|
|
|
|
|
/* lock otg_master_update to process all pipes associated with
|
|
|
|
* this OTG. this is done only one time.
|
|
|
|
*/
|
2017-06-03 08:00:45 +09:00
|
|
|
/* watermark is for all pipes */
|
2017-07-24 07:30:15 +09:00
|
|
|
program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-07-15 03:07:16 +09:00
|
|
|
/* pstate stuck check after watermark update */
|
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
|
|
|
|
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_global_sync(
|
|
|
|
pipe_ctx->stream_res.tg);
|
|
|
|
pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
|
2017-06-03 08:00:45 +09:00
|
|
|
}
|
2017-05-03 06:01:10 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state != NULL) {
|
2017-06-03 08:00:45 +09:00
|
|
|
dcn10_power_on_fe(dc, pipe_ctx, context);
|
2017-08-05 04:42:36 +09:00
|
|
|
|
|
|
|
/* temporary dcn1 wa:
|
|
|
|
* watermark update requires toggle after a/b/c/d sets are programmed
|
|
|
|
* if hubp is pg then wm value doesn't get properaged to hubp
|
|
|
|
* need to toggle after ungate to ensure wm gets to hubp.
|
|
|
|
*
|
|
|
|
* final solution: we need to get SMU to do the toggle as
|
|
|
|
* DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
|
|
|
|
* both driver and fw accessing same register
|
|
|
|
*/
|
|
|
|
toggle_watermark_change_req(dc->hwseq);
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
update_dchubp_dpp(dc, pipe_ctx, context);
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-07-15 03:07:16 +09:00
|
|
|
/* pstate stuck check after each pipe is programmed */
|
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (pipe_ctx->bottom_pipe != NULL)
|
|
|
|
program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_pplib_apply_display_requirements(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct validate_context *context)
|
|
|
|
{
|
|
|
|
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
|
|
|
|
|
|
|
|
pp_display_cfg->all_displays_in_sync = false;/*todo*/
|
|
|
|
pp_display_cfg->nb_pstate_switch_disable = false;
|
2017-05-04 00:40:40 +09:00
|
|
|
pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
|
|
|
|
pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
|
|
|
|
pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
|
|
|
|
pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
pp_display_cfg->avail_mclk_switch_time_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
|
2017-05-09 04:19:06 +09:00
|
|
|
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
|
|
|
|
pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
|
|
|
|
pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
dce110_fill_display_configs(context, pp_display_cfg);
|
|
|
|
|
|
|
|
if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
|
|
|
|
struct dm_pp_display_configuration)) != 0)
|
|
|
|
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
|
|
|
|
|
|
|
|
dc->prev_display_config = *pp_display_cfg;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_apply_ctx_for_surface(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-08-03 13:22:25 +09:00
|
|
|
const struct dc_stream_state *stream,
|
|
|
|
int num_planes,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct validate_context *context)
|
|
|
|
{
|
2017-07-20 09:22:22 +09:00
|
|
|
int i, be_idx;
|
2017-05-09 04:19:06 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
|
2017-08-03 13:22:25 +09:00
|
|
|
be_idx = -1;
|
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
if (stream == context->res_ctx.pipe_ctx[i].stream) {
|
|
|
|
be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
|
2017-07-20 09:22:22 +09:00
|
|
|
break;
|
2017-08-03 13:22:25 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ASSERT(be_idx != -1);
|
|
|
|
|
|
|
|
if (num_planes == 0) {
|
|
|
|
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
|
|
|
struct pipe_ctx *old_pipe_ctx =
|
|
|
|
&dc->current_context->res_ctx.pipe_ctx[i];
|
|
|
|
|
2017-08-12 00:23:30 +09:00
|
|
|
if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
|
|
|
|
old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
|
2017-08-03 13:22:25 +09:00
|
|
|
dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx);
|
2017-08-12 00:23:30 +09:00
|
|
|
}
|
2017-08-03 13:22:25 +09:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
/* reset unused mpcc */
|
2017-07-13 07:38:04 +09:00
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
2017-06-15 07:58:04 +09:00
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
struct pipe_ctx *old_pipe_ctx =
|
|
|
|
&dc->current_context->res_ctx.pipe_ctx[i];
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
|
2017-07-20 09:22:22 +09:00
|
|
|
continue;
|
|
|
|
|
2017-07-19 04:50:47 +09:00
|
|
|
/*
|
|
|
|
* Powergate reused pipes that are not powergated
|
|
|
|
* fairly hacky right now, using opp_id as indicator
|
|
|
|
*/
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
|
2017-07-31 02:59:26 +09:00
|
|
|
if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
|
2017-07-19 04:50:47 +09:00
|
|
|
dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
|
2017-07-21 05:17:17 +09:00
|
|
|
/*
|
|
|
|
* power down fe will unlock when calling reset, need
|
|
|
|
* to lock it back here. Messy, need rework.
|
|
|
|
*/
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
|
2017-07-21 05:17:17 +09:00
|
|
|
}
|
2017-07-19 04:50:47 +09:00
|
|
|
}
|
2017-06-15 07:58:04 +09:00
|
|
|
|
2017-07-20 09:22:22 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
|
2017-06-15 07:58:04 +09:00
|
|
|
|| (!pipe_ctx->stream && old_pipe_ctx->stream)) {
|
2017-07-31 02:59:26 +09:00
|
|
|
if (old_pipe_ctx->stream_res.tg->inst != be_idx)
|
2017-07-20 09:22:22 +09:00
|
|
|
continue;
|
|
|
|
|
2017-07-13 07:38:04 +09:00
|
|
|
if (!old_pipe_ctx->top_pipe) {
|
|
|
|
ASSERT(0);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2017-07-19 04:50:47 +09:00
|
|
|
/* reset mpc */
|
2017-07-22 06:46:50 +09:00
|
|
|
dc->res_pool->mpc->funcs->remove(
|
|
|
|
dc->res_pool->mpc,
|
2017-07-31 02:55:28 +09:00
|
|
|
old_pipe_ctx->stream_res.opp,
|
2017-07-22 06:46:50 +09:00
|
|
|
old_pipe_ctx->pipe_idx);
|
2017-07-31 02:55:28 +09:00
|
|
|
old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true;
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-07-24 23:47:02 +09:00
|
|
|
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
|
|
|
|
"[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
|
|
|
|
old_pipe_ctx->mpcc->inst);*/
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
|
2017-06-15 07:58:04 +09:00
|
|
|
old_pipe_ctx->top_pipe = NULL;
|
|
|
|
old_pipe_ctx->bottom_pipe = NULL;
|
2017-07-27 22:55:38 +09:00
|
|
|
old_pipe_ctx->plane_state = NULL;
|
2017-06-15 07:58:04 +09:00
|
|
|
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_DC,
|
|
|
|
"Reset mpcc for pipe %d\n",
|
|
|
|
old_pipe_ctx->pipe_idx);
|
|
|
|
}
|
2017-07-13 07:38:04 +09:00
|
|
|
}
|
2017-06-15 07:58:04 +09:00
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
|
|
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
|
|
|
|
2017-08-03 13:22:25 +09:00
|
|
|
if (pipe_ctx->stream != stream)
|
2017-05-09 04:19:06 +09:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* looking for top pipe to program */
|
2017-06-02 07:35:54 +09:00
|
|
|
if (!pipe_ctx->top_pipe)
|
2017-05-09 04:19:06 +09:00
|
|
|
program_all_pipe_in_tree(dc, pipe_ctx, context);
|
|
|
|
}
|
|
|
|
|
2017-06-08 02:53:30 +09:00
|
|
|
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\n============== Watermark parameters ==============\n"
|
|
|
|
"a.urgent_ns: %d \n"
|
|
|
|
"a.cstate_enter_plus_exit: %d \n"
|
|
|
|
"a.cstate_exit: %d \n"
|
|
|
|
"a.pstate_change: %d \n"
|
|
|
|
"a.pte_meta_urgent: %d \n"
|
|
|
|
"b.urgent_ns: %d \n"
|
|
|
|
"b.cstate_enter_plus_exit: %d \n"
|
|
|
|
"b.cstate_exit: %d \n"
|
|
|
|
"b.pstate_change: %d \n"
|
|
|
|
"b.pte_meta_urgent: %d \n",
|
|
|
|
context->bw.dcn.watermarks.a.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.b.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.b.pte_meta_urgent_ns
|
|
|
|
);
|
|
|
|
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
|
|
|
"\nc.urgent_ns: %d \n"
|
|
|
|
"c.cstate_enter_plus_exit: %d \n"
|
|
|
|
"c.cstate_exit: %d \n"
|
|
|
|
"c.pstate_change: %d \n"
|
|
|
|
"c.pte_meta_urgent: %d \n"
|
|
|
|
"d.urgent_ns: %d \n"
|
|
|
|
"d.cstate_enter_plus_exit: %d \n"
|
|
|
|
"d.cstate_exit: %d \n"
|
|
|
|
"d.pstate_change: %d \n"
|
|
|
|
"d.pte_meta_urgent: %d \n"
|
|
|
|
"========================================================\n",
|
|
|
|
context->bw.dcn.watermarks.c.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.d.urgent_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
|
|
|
|
context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
|
|
|
|
context->bw.dcn.watermarks.d.pte_meta_urgent_ns
|
|
|
|
);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks)
|
2017-07-15 03:07:16 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dcn10_set_bandwidth(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct validate_context *context,
|
|
|
|
bool decrease_allowed)
|
|
|
|
{
|
|
|
|
struct dm_pp_clock_for_voltage_req clock;
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
|
|
|
return;
|
|
|
|
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
|
|
|
|
> dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
|
2017-05-09 04:19:06 +09:00
|
|
|
dc->res_pool->display_clock->funcs->set_clock(
|
|
|
|
dc->res_pool->display_clock,
|
2017-05-03 06:29:48 +09:00
|
|
|
context->bw.dcn.calc_clk.dispclk_khz);
|
2017-05-04 00:40:40 +09:00
|
|
|
dc->current_context->bw.dcn.cur_clk.dispclk_khz =
|
|
|
|
context->bw.dcn.calc_clk.dispclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
|
|
|
|
> dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
|
2017-05-09 04:19:06 +09:00
|
|
|
clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
|
2017-05-03 06:29:48 +09:00
|
|
|
clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
|
2017-05-04 00:40:40 +09:00
|
|
|
dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
|
|
|
|
context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
2017-05-04 00:40:40 +09:00
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
|
|
|
|
> dc->current_context->bw.dcn.cur_clk.fclk_khz) {
|
2017-05-09 04:19:06 +09:00
|
|
|
clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
|
2017-05-03 06:29:48 +09:00
|
|
|
clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
|
2017-05-09 04:19:06 +09:00
|
|
|
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
|
2017-05-03 06:29:48 +09:00
|
|
|
dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
|
2017-05-04 00:40:40 +09:00
|
|
|
context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
|
|
|
|
}
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
|
|
|
|
> dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
|
|
|
|
dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
|
|
|
|
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
|
|
|
|
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
|
|
|
|
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
|
|
|
|
}
|
|
|
|
/* Decrease in freq is increase in period so opposite comparison for dram_ccm */
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
|
|
|
|
< dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {
|
|
|
|
dc->current_context->bw.dcn.calc_clk.dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.dram_ccm_us;
|
|
|
|
context->bw.dcn.cur_clk.dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.dram_ccm_us;
|
|
|
|
}
|
|
|
|
if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
|
|
|
|
< dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) {
|
|
|
|
dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.min_active_dram_ccm_us;
|
|
|
|
context->bw.dcn.cur_clk.min_active_dram_ccm_us =
|
|
|
|
context->bw.dcn.calc_clk.min_active_dram_ccm_us;
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
dcn10_pplib_apply_display_requirements(dc, context);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-15 03:07:16 +09:00
|
|
|
/* need to fix this function. not doing the right thing here */
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_drr(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes, int vmin, int vmax)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
struct drr_params params = {0};
|
|
|
|
|
|
|
|
params.vertical_total_max = vmax;
|
|
|
|
params.vertical_total_min = vmin;
|
|
|
|
|
|
|
|
/* TODO: If multiple pipes are to be supported, you need
|
|
|
|
* some GSL stuff
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_pipes; i++) {
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void get_position(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes,
|
|
|
|
struct crtc_position *position)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
/* TODO: handle pipes > 1
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_pipes; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
|
|
|
|
int num_pipes, const struct dc_static_screen_events *events)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
unsigned int value = 0;
|
|
|
|
|
|
|
|
if (events->surface_update)
|
|
|
|
value |= 0x80;
|
|
|
|
if (events->cursor_update)
|
|
|
|
value |= 0x2;
|
|
|
|
|
|
|
|
for (i = 0; i < num_pipes; i++)
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx[i]->stream_res.tg->funcs->
|
|
|
|
set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
|
2017-05-09 04:19:06 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_plane_config(
|
2017-08-02 04:00:25 +09:00
|
|
|
const struct dc *dc,
|
2017-05-09 04:19:06 +09:00
|
|
|
struct pipe_ctx *pipe_ctx,
|
|
|
|
struct resource_context *res_ctx)
|
|
|
|
{
|
|
|
|
/* TODO */
|
|
|
|
program_gamut_remap(pipe_ctx);
|
|
|
|
}
|
|
|
|
|
2017-07-07 04:42:04 +09:00
|
|
|
static void dcn10_config_stereo_parameters(
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
|
2017-06-09 05:55:02 +09:00
|
|
|
{
|
2017-07-26 09:51:26 +09:00
|
|
|
enum view_3d_format view_format = stream->view_format;
|
2017-06-09 05:55:02 +09:00
|
|
|
enum dc_timing_3d_format timing_3d_format =\
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->timing.timing_3d_format;
|
2017-06-09 05:55:02 +09:00
|
|
|
bool non_stereo_timing = false;
|
|
|
|
|
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
|
|
|
|
non_stereo_timing = true;
|
|
|
|
|
|
|
|
if (non_stereo_timing == false &&
|
|
|
|
view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
|
|
|
|
|
|
|
|
flags->PROGRAM_STEREO = 1;
|
|
|
|
flags->PROGRAM_POLARITY = 1;
|
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
|
|
|
|
timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
|
|
|
|
enum display_dongle_type dongle = \
|
2017-07-23 09:05:20 +09:00
|
|
|
stream->sink->link->ddc->dongle_type;
|
2017-06-09 05:55:02 +09:00
|
|
|
if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
|
|
|
|
dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
|
|
|
|
dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
|
|
|
|
flags->DISABLE_STEREO_DP_SYNC = 1;
|
|
|
|
}
|
|
|
|
flags->RIGHT_EYE_POLARITY =\
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->timing.flags.RIGHT_EYE_3D_POLARITY;
|
2017-06-09 05:55:02 +09:00
|
|
|
if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
|
|
|
|
flags->FRAME_PACKED = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
|
2017-06-09 05:55:02 +09:00
|
|
|
{
|
|
|
|
struct crtc_stereo_flags flags = { 0 };
|
2017-07-27 22:33:33 +09:00
|
|
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
2017-06-09 05:55:02 +09:00
|
|
|
|
|
|
|
dcn10_config_stereo_parameters(stream, &flags);
|
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
|
|
|
|
pipe_ctx->stream_res.opp,
|
2017-06-09 05:55:02 +09:00
|
|
|
flags.PROGRAM_STEREO == 1 ? true:false,
|
2017-07-26 09:51:26 +09:00
|
|
|
stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
|
2017-06-09 05:55:02 +09:00
|
|
|
|
2017-07-31 02:59:26 +09:00
|
|
|
pipe_ctx->stream_res.tg->funcs->program_stereo(
|
|
|
|
pipe_ctx->stream_res.tg,
|
2017-07-26 09:51:26 +09:00
|
|
|
&stream->timing,
|
2017-06-09 05:55:02 +09:00
|
|
|
&flags);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-07-24 23:47:02 +09:00
|
|
|
static void dcn10_wait_for_mpcc_disconnect(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-07-24 23:47:02 +09:00
|
|
|
struct resource_pool *res_pool,
|
|
|
|
struct pipe_ctx *pipe_ctx)
|
2017-07-24 04:18:57 +09:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-31 02:55:28 +09:00
|
|
|
if (!pipe_ctx->stream_res.opp)
|
2017-07-24 23:47:02 +09:00
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
2017-07-31 02:55:28 +09:00
|
|
|
if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
|
2017-07-22 06:46:50 +09:00
|
|
|
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
|
2017-07-31 02:55:28 +09:00
|
|
|
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
|
2017-07-24 23:47:02 +09:00
|
|
|
res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true);
|
|
|
|
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
|
|
|
|
"[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
|
|
|
|
i);*/
|
2017-07-24 04:18:57 +09:00
|
|
|
}
|
|
|
|
}
|
2017-07-24 23:47:02 +09:00
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
if (dc->debug.sanity_checks) {
|
2017-08-04 03:20:14 +09:00
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-24 04:18:57 +09:00
|
|
|
}
|
|
|
|
|
2017-07-07 04:42:04 +09:00
|
|
|
static bool dcn10_dummy_display_power_gating(
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc,
|
2017-07-07 04:42:04 +09:00
|
|
|
uint8_t controller_id,
|
|
|
|
struct dc_bios *dcb,
|
2017-07-15 03:07:16 +09:00
|
|
|
enum pipe_gating_control power_gating)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
|
|
|
|
{
|
2017-07-27 22:55:38 +09:00
|
|
|
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
|
2017-07-31 02:59:26 +09:00
|
|
|
struct timing_generator *tg = pipe_ctx->stream_res.tg;
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state->ctx->dc->debug.sanity_checks) {
|
2017-08-02 04:00:25 +09:00
|
|
|
struct dc *dc = plane_state->ctx->dc;
|
2017-07-15 03:07:16 +09:00
|
|
|
|
|
|
|
verify_allow_pstate_change_high(dc->hwseq);
|
|
|
|
}
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
if (plane_state == NULL)
|
2017-07-15 03:07:16 +09:00
|
|
|
return;
|
|
|
|
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->status.is_flip_pending =
|
2017-07-31 00:55:55 +09:00
|
|
|
pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
|
|
|
|
pipe_ctx->plane_res.mi);
|
2017-07-15 03:07:16 +09:00
|
|
|
|
2017-07-31 00:55:55 +09:00
|
|
|
plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
|
|
|
|
if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
|
2017-07-15 03:07:16 +09:00
|
|
|
tg->funcs->is_stereo_left_eye) {
|
2017-07-27 22:55:38 +09:00
|
|
|
plane_state->status.is_right_eye =
|
2017-07-31 02:59:26 +09:00
|
|
|
!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
|
2017-07-15 03:07:16 +09:00
|
|
|
}
|
|
|
|
}
|
2017-07-07 04:42:04 +09:00
|
|
|
|
2017-08-15 07:17:01 +09:00
|
|
|
|
|
|
|
|
2017-05-09 04:19:06 +09:00
|
|
|
static const struct hw_sequencer_funcs dcn10_funcs = {
|
2017-06-03 06:25:49 +09:00
|
|
|
.program_gamut_remap = program_gamut_remap,
|
2017-06-29 06:21:42 +09:00
|
|
|
.program_csc_matrix = program_csc_matrix,
|
2017-07-08 06:21:45 +09:00
|
|
|
.init_hw = dcn10_init_hw,
|
2017-05-09 04:19:06 +09:00
|
|
|
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
|
|
|
|
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
|
|
|
|
.set_plane_config = set_plane_config,
|
2017-08-03 23:19:58 +09:00
|
|
|
.update_plane_addr = dcn10_update_plane_addr,
|
2017-07-24 07:30:15 +09:00
|
|
|
.update_dchub = dcn10_update_dchub,
|
2017-07-15 03:07:16 +09:00
|
|
|
.update_pending_status = dcn10_update_pending_status,
|
2017-05-09 04:19:06 +09:00
|
|
|
.set_input_transfer_func = dcn10_set_input_transfer_func,
|
|
|
|
.set_output_transfer_func = dcn10_set_output_transfer_func,
|
|
|
|
.power_down = dce110_power_down,
|
|
|
|
.enable_accelerated_mode = dce110_enable_accelerated_mode,
|
|
|
|
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
|
|
|
|
.update_info_frame = dce110_update_info_frame,
|
|
|
|
.enable_stream = dce110_enable_stream,
|
|
|
|
.disable_stream = dce110_disable_stream,
|
|
|
|
.unblank_stream = dce110_unblank_stream,
|
2017-07-07 04:42:04 +09:00
|
|
|
.enable_display_power_gating = dcn10_dummy_display_power_gating,
|
2017-05-09 04:19:06 +09:00
|
|
|
.power_down_front_end = dcn10_power_down_fe,
|
|
|
|
.power_on_front_end = dcn10_power_on_fe,
|
|
|
|
.pipe_control_lock = dcn10_pipe_control_lock,
|
|
|
|
.set_bandwidth = dcn10_set_bandwidth,
|
|
|
|
.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
|
|
|
|
.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
|
|
|
|
.set_drr = set_drr,
|
|
|
|
.get_position = get_position,
|
2017-06-09 05:55:02 +09:00
|
|
|
.set_static_screen_control = set_static_screen_control,
|
2017-07-18 05:04:02 +09:00
|
|
|
.setup_stereo = dcn10_setup_stereo,
|
|
|
|
.set_avmute = dce110_set_avmute,
|
2017-07-24 04:18:57 +09:00
|
|
|
.log_hw_state = dcn10_log_hw_state,
|
|
|
|
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect
|
2017-05-09 04:19:06 +09:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2017-08-02 04:00:25 +09:00
|
|
|
void dcn10_hw_sequencer_construct(struct dc *dc)
|
2017-05-09 04:19:06 +09:00
|
|
|
{
|
|
|
|
dc->hwss = dcn10_funcs;
|
|
|
|
}
|
|
|
|
|