drm/amd/display: fix mpo exit hang
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -500,8 +500,10 @@ static void reset_front_end(
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HUBP_CLOCK_ENABLE, 0);
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REG_UPDATE(DPP_CONTROL[fe_idx],
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DPP_CLOCK_ENABLE, 0);
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REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
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OPP_PIPE_CLOCK_EN, 0);
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if (mpcc_cfg.top_of_tree)
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REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
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OPP_PIPE_CLOCK_EN, 0);
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xfm->funcs->transform_reset(xfm);
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@ -1584,7 +1586,7 @@ static void dcn10_apply_ctx_for_surface(
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int i;
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/* reset unused mpcc */
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/*for (i = 0; i < dc->res_pool->pipe_count; i++) {
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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struct pipe_ctx *old_pipe_ctx =
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&dc->current_context->res_ctx.pipe_ctx[i];
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@ -1593,7 +1595,12 @@ static void dcn10_apply_ctx_for_surface(
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|| (!pipe_ctx->stream && old_pipe_ctx->stream)) {
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struct mpcc_cfg mpcc_cfg;
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mpcc_cfg.opp_id = 0xf;
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if (!old_pipe_ctx->top_pipe) {
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ASSERT(0);
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continue;
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}
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mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id;
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mpcc_cfg.top_dpp_id = 0xf;
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mpcc_cfg.bot_mpcc_id = 0xf;
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mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
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@ -1607,7 +1614,7 @@ static void dcn10_apply_ctx_for_surface(
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"Reset mpcc for pipe %d\n",
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old_pipe_ctx->pipe_idx);
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}
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}*/
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}
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if (!surface)
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return;
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