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![]() For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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.. | ||
boot-mode.c | ||
clkrst_init.c | ||
ddrphy_init.c | ||
early_clkrst_init.c | ||
lowlevel_debug.S | ||
Makefile | ||
pinctrl.c | ||
platdevice.c | ||
pll_init.c | ||
pll_spectrum.c | ||
sbc_init.c | ||
sg_init.c | ||
umc_init.c |