brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-09-30 00:20:44 +09:00
Code Issues Projects Releases Wiki Activity

ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*

Browse Source 
Follow the register macros in the LSI specification book.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada 2015-02-27 02:26:50 +09:00
parent 27eac5df17
commit f267b81e20
5 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-uniphier/include/mach/sc-regs.h
View File

@ -47,12 +47,12 @@
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)

4
arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
View File

@ -22,8 +22,8 @@ void clkrst_init(void)
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

4
arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
View File

@ -22,8 +22,8 @@ void clkrst_init(void)
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

2
arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
View File

@ -17,7 +17,7 @@
ENTRY(setup_lowlevel_debug)
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CLK_PERI
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
init_debug_uart r0, r1, r2

4
arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
View File

@ -22,8 +22,8 @@ void clkrst_init(void)
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}