mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-31 07:13:44 +09:00
d1cd045982
On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
139 lines
2.7 KiB
C
139 lines
2.7 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/u-boot-x86.h>
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#include <flash.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/post.h>
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#include <asm/arch-coreboot/tables.h>
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#include <asm/arch-coreboot/sysinfo.h>
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#include <asm/arch/timestamp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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int ret = get_coreboot_info(&lib_sysinfo);
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if (ret != 0) {
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printf("Failed to parse coreboot tables.\n");
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return ret;
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}
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timestamp_init();
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return x86_cpu_init_f();
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_early_init_r(void)
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{
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/* CPU Speed to 100MHz */
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gd->cpu_clk = 100000000;
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/* Crystal is 33.000MHz */
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gd->bus_clk = 33000000;
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return 0;
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}
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void show_boot_progress(int val)
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{
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#if MIN_PORT80_KCLOCKS_DELAY
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/*
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* Scale the time counter reading to avoid using 64 bit arithmetics.
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* Can't use get_timer() here becuase it could be not yet
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* initialized or even implemented.
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*/
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if (!gd->arch.tsc_prev) {
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gd->arch.tsc_base_kclocks = rdtsc() / 1000;
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gd->arch.tsc_prev = 0;
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} else {
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uint32_t now;
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do {
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now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
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} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
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gd->arch.tsc_prev = now;
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}
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#endif
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outb(val, POST_PORT);
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}
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int print_cpuinfo(void)
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{
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return default_print_cpuinfo();
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}
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int last_stage_init(void)
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{
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if (gd->flags & GD_FLG_COLD_BOOT)
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timestamp_add_to_bootstage();
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return 0;
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}
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#ifndef CONFIG_SYS_NO_FLASH
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#define MTRR_TYPE_WP 5
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#define MTRRcap_MSR 0xfe
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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void board_final_cleanup(void)
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{
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/* Un-cache the ROM so the kernel has one
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* more MTRR available.
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*
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* Coreboot should have assigned this to the
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* top available variable MTRR.
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*/
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u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
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u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
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/* Make sure this MTRR is the correct Write-Protected type */
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if (top_type == MTRR_TYPE_WP) {
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disable_caches();
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wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
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wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
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enable_caches();
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}
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/* Issue SMI to Coreboot to lock down ME and registers */
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printf("Finalizing Coreboot\n");
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outb(0xcb, 0xb2);
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}
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void panic_puts(const char *str)
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{
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NS16550_t port = (NS16550_t)0x3f8;
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NS16550_init(port, 1);
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while (*str)
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NS16550_putc(port, *str++);
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}
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