Simon Glass d1cd045982 x86: Emit post codes in startup code for Chromebooks ... On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2014-11-21 07:34:11 +01:00
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coreboot	x86: Emit post codes in startup code for Chromebooks	2014-11-21 07:34:11 +01:00
ivybridge	x86: Add chromebook_link board	2014-11-21 07:34:11 +01:00
call64.S	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
config.mk	kconfig: delete redundant CONFIG_${ARCH} definition	2014-07-30 14:42:02 -04:00
cpu.c	x86: Replace fill_processor_name() with cpu_get_name()	2014-11-21 07:24:12 +01:00
interrupts.c	x86: Fix up some missing prototypes	2014-11-21 07:24:09 +01:00
Makefile	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
resetvec.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
start16.S	x86: Save the BIST value on reset	2014-11-21 07:24:10 +01:00
start.S	x86: Emit post codes in startup code for Chromebooks	2014-11-21 07:34:11 +01:00
u-boot.lds	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00