u-boot-brain/arch/x86
Simon Glass d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
..
cpu x86: Emit post codes in startup code for Chromebooks 2014-11-21 07:34:11 +01:00
dts x86: Add chromebook_link board 2014-11-21 07:34:11 +01:00
include/asm x86: Emit post codes in startup code for Chromebooks 2014-11-21 07:34:11 +01:00
lib x86: Allow timer calibration to work on ivybridge 2014-11-21 07:24:12 +01:00
config.mk x86: Remove REALMODE_BASE which is no longer used 2014-11-21 07:24:08 +01:00
Kconfig x86: Build a .rom file which can be flashed to an x86 machine 2014-11-21 07:34:11 +01:00