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![York Sun](/assets/img/avatar_default.png)
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
714 lines
21 KiB
C
714 lines
21 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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/*
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* Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
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* Based on code from spd_sdram.c
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* Author: James Yang [at freescale.com]
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#include "ddr.h"
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void fsl_ddr_set_lawbar(
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const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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void fsl_ddr_set_intl3r(const unsigned int granule_size);
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#if defined(SPD_EEPROM_ADDRESS) || \
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defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
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defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
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#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS,
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};
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#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
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[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
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};
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#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
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[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
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};
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#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
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[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
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[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
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[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
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};
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#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
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[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
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[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
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};
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#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
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u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
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[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
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[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
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[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
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[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
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[2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
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[2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
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};
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#endif
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static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
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{
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int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
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sizeof(generic_spd_eeprom_t));
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if (ret) {
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if (i2c_address ==
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#ifdef SPD_EEPROM_ADDRESS
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SPD_EEPROM_ADDRESS
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#elif defined(SPD_EEPROM_ADDRESS1)
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SPD_EEPROM_ADDRESS1
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#endif
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) {
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printf("DDR: failed to read SPD from address %u\n",
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i2c_address);
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} else {
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debug("DDR: failed to read SPD from address %u\n",
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i2c_address);
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}
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memset(spd, 0, sizeof(generic_spd_eeprom_t));
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}
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}
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__attribute__((weak, alias("__get_spd")))
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void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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i2c_address = spd_i2c_addr[ctrl_num][i];
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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#else
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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}
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#endif /* SPD_EEPROM_ADDRESSx */
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/*
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* ASSUMPTIONS:
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* - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
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* - Same memory data bus width on all controllers
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*
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* NOTES:
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*
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* The memory controller and associated documentation use confusing
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* terminology when referring to the orgranization of DRAM.
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*
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* Here is a terminology translation table:
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*
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* memory controller/documention |industry |this code |signals
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* -------------------------------|-----------|-----------|-----------------
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* physical bank/bank |rank |rank |chip select (CS)
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* logical bank/sub-bank |bank |bank |bank address (BA)
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* page/row |row |page |row address
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* ??? |column |column |column address
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*
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* The naming confusion is further exacerbated by the descriptions of the
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* memory controller interleaving feature, where accesses are interleaved
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* _BETWEEN_ two seperate memory controllers. This is configured only in
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* CS0_CONFIG[INTLV_CTL] of each memory controller.
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*
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* memory controller documentation | number of chip selects
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* | per memory controller supported
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* --------------------------------|-----------------------------------------
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* cache line interleaving | 1 (CS0 only)
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* page interleaving | 1 (CS0 only)
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* bank interleaving | 1 (CS0 only)
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* superbank interleraving | depends on bank (chip select)
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* | interleraving [rank interleaving]
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* | mode used on every memory controller
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*
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* Even further confusing is the existence of the interleaving feature
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* _WITHIN_ each memory controller. The feature is referred to in
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* documentation as chip select interleaving or bank interleaving,
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* although it is configured in the DDR_SDRAM_CFG field.
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*
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* Name of field | documentation name | this code
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* -----------------------------|-----------------------|------------------
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* DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
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* | interleaving
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*/
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const char *step_string_tbl[] = {
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"STEP_GET_SPD",
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"STEP_COMPUTE_DIMM_PARMS",
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"STEP_COMPUTE_COMMON_PARMS",
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"STEP_GATHER_OPTS",
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"STEP_ASSIGN_ADDRESSES",
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"STEP_COMPUTE_REGS",
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"STEP_PROGRAM_REGS",
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"STEP_ALL"
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};
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const char * step_to_string(unsigned int step) {
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unsigned int s = __ilog2(step);
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if ((1 << s) != step)
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return step_string_tbl[7];
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return step_string_tbl[s];
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}
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static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
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unsigned int dbw_cap_adj[])
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{
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int i, j;
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unsigned long long total_mem, current_mem_base, total_ctlr_mem;
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unsigned long long rank_density, ctlr_density = 0;
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/*
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* If a reduced data width is requested, but the SPD
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* specifies a physically wider device, adjust the
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* computed dimm capacities accordingly before
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* assigning addresses.
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*/
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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unsigned int found = 0;
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switch (pinfo->memctl_opts[i].data_bus_width) {
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case 2:
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/* 16-bit */
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned int dw;
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if (!pinfo->dimm_params[i][j].n_ranks)
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continue;
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dw = pinfo->dimm_params[i][j].primary_sdram_width;
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if ((dw == 72 || dw == 64)) {
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dbw_cap_adj[i] = 2;
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break;
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} else if ((dw == 40 || dw == 32)) {
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dbw_cap_adj[i] = 1;
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break;
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}
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}
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break;
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case 1:
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/* 32-bit */
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned int dw;
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dw = pinfo->dimm_params[i][j].data_width;
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if (pinfo->dimm_params[i][j].n_ranks
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&& (dw == 72 || dw == 64)) {
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/*
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* FIXME: can't really do it
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* like this because this just
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* further reduces the memory
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*/
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found = 1;
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break;
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}
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}
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if (found) {
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dbw_cap_adj[i] = 1;
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}
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break;
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case 0:
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/* 64-bit */
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break;
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default:
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printf("unexpected data bus width "
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"specified controller %u\n", i);
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return 1;
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}
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debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
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}
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current_mem_base = 0ull;
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total_mem = 0;
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if (pinfo->memctl_opts[0].memctl_interleaving) {
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rank_density = pinfo->dimm_params[0][0].rank_density >>
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dbw_cap_adj[0];
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switch (pinfo->memctl_opts[0].ba_intlv_ctl &
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FSL_DDR_CS0_CS1_CS2_CS3) {
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case FSL_DDR_CS0_CS1_CS2_CS3:
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ctlr_density = 4 * rank_density;
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break;
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case FSL_DDR_CS0_CS1:
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case FSL_DDR_CS0_CS1_AND_CS2_CS3:
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ctlr_density = 2 * rank_density;
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break;
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case FSL_DDR_CS2_CS3:
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default:
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ctlr_density = rank_density;
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break;
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}
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
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rank_density, ctlr_density);
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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if (pinfo->memctl_opts[i].memctl_interleaving) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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total_ctlr_mem = 2 * ctlr_density;
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break;
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case FSL_DDR_3WAY_1KB_INTERLEAVING:
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case FSL_DDR_3WAY_4KB_INTERLEAVING:
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case FSL_DDR_3WAY_8KB_INTERLEAVING:
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total_ctlr_mem = 3 * ctlr_density;
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break;
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case FSL_DDR_4WAY_1KB_INTERLEAVING:
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case FSL_DDR_4WAY_4KB_INTERLEAVING:
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case FSL_DDR_4WAY_8KB_INTERLEAVING:
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total_ctlr_mem = 4 * ctlr_density;
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break;
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default:
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panic("Unknown interleaving mode");
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}
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem = current_mem_base + total_ctlr_mem;
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debug("ctrl %d base 0x%llx\n", i, current_mem_base);
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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} else {
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/* when 3rd controller not interleaved */
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current_mem_base = total_mem;
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total_ctlr_mem = 0;
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned long long cap =
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pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
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pinfo->dimm_params[i][j].base_address =
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current_mem_base;
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debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
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current_mem_base += cap;
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total_ctlr_mem += cap;
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}
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem += total_ctlr_mem;
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}
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}
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} else {
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/*
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* Simple linear assignment if memory
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* controllers are not interleaved.
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*/
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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total_ctlr_mem = 0;
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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/* Compute DIMM base addresses. */
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unsigned long long cap =
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pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
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pinfo->dimm_params[i][j].base_address =
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current_mem_base;
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debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
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current_mem_base += cap;
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total_ctlr_mem += cap;
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}
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem += total_ctlr_mem;
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}
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}
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debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
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return total_mem;
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}
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/* Use weak function to allow board file to override the address assignment */
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__attribute__((weak, alias("__step_assign_addresses")))
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unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
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unsigned int dbw_cap_adj[]);
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unsigned long long
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fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
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unsigned int size_only)
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{
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unsigned int i, j;
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unsigned long long total_mem = 0;
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int assert_reset;
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fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
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common_timing_params_t *timing_params = pinfo->common_timing_params;
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assert_reset = board_need_mem_reset();
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/* data bus width capacity adjust shift amount */
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unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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dbw_capacity_adjust[i] = 0;
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}
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debug("starting at step %u (%s)\n",
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start_step, step_to_string(start_step));
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switch (start_step) {
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case STEP_GET_SPD:
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#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
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/* STEP 1: Gather all DIMM SPD data */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
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}
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case STEP_COMPUTE_DIMM_PARMS:
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/* STEP 2: Compute DIMM parameters from SPD data */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned int retval;
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generic_spd_eeprom_t *spd =
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&(pinfo->spd_installed_dimms[i][j]);
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dimm_params_t *pdimm =
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&(pinfo->dimm_params[i][j]);
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retval = compute_dimm_parameters(spd, pdimm, i);
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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if (!i && !j && retval) {
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printf("SPD error on controller %d! "
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"Trying fallback to raw timing "
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"calculation\n", i);
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fsl_ddr_get_dimm_params(pdimm, i, j);
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}
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#else
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if (retval == 2) {
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printf("Error: compute_dimm_parameters"
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" non-zero returned FATAL value "
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"for memctl=%u dimm=%u\n", i, j);
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return 0;
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}
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#endif
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if (retval) {
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debug("Warning: compute_dimm_parameters"
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" non-zero return value for memctl=%u "
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"dimm=%u\n", i, j);
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}
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}
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}
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#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
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case STEP_COMPUTE_DIMM_PARMS:
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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dimm_params_t *pdimm =
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&(pinfo->dimm_params[i][j]);
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fsl_ddr_get_dimm_params(pdimm, i, j);
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}
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}
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debug("Filling dimm parameters from board specific file\n");
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#endif
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case STEP_COMPUTE_COMMON_PARMS:
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/*
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* STEP 3: Compute a common set of timing parameters
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* suitable for all of the DIMMs on each memory controller
|
|
*/
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
debug("Computing lowest common DIMM"
|
|
" parameters for memctl=%u\n", i);
|
|
compute_lowest_common_dimm_parameters(
|
|
pinfo->dimm_params[i],
|
|
&timing_params[i],
|
|
CONFIG_DIMM_SLOTS_PER_CTLR);
|
|
}
|
|
|
|
case STEP_GATHER_OPTS:
|
|
/* STEP 4: Gather configuration requirements from user */
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
debug("Reloading memory controller "
|
|
"configuration options for memctl=%u\n", i);
|
|
/*
|
|
* This "reloads" the memory controller options
|
|
* to defaults. If the user "edits" an option,
|
|
* next_step points to the step after this,
|
|
* which is currently STEP_ASSIGN_ADDRESSES.
|
|
*/
|
|
populate_memctl_options(
|
|
timing_params[i].all_DIMMs_registered,
|
|
&pinfo->memctl_opts[i],
|
|
pinfo->dimm_params[i], i);
|
|
/*
|
|
* For RDIMMs, JEDEC spec requires clocks to be stable
|
|
* before reset signal is deasserted. For the boards
|
|
* using fixed parameters, this function should be
|
|
* be called from board init file.
|
|
*/
|
|
if (timing_params[i].all_DIMMs_registered)
|
|
assert_reset = 1;
|
|
}
|
|
if (assert_reset) {
|
|
debug("Asserting mem reset\n");
|
|
board_assert_mem_reset();
|
|
}
|
|
|
|
case STEP_ASSIGN_ADDRESSES:
|
|
/* STEP 5: Assign addresses to chip selects */
|
|
check_interleaving_options(pinfo);
|
|
total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
|
|
|
|
case STEP_COMPUTE_REGS:
|
|
/* STEP 6: compute controller register values */
|
|
debug("FSL Memory ctrl register computation\n");
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
if (timing_params[i].ndimms_present == 0) {
|
|
memset(&ddr_reg[i], 0,
|
|
sizeof(fsl_ddr_cfg_regs_t));
|
|
continue;
|
|
}
|
|
|
|
compute_fsl_memctl_config_regs(
|
|
&pinfo->memctl_opts[i],
|
|
&ddr_reg[i], &timing_params[i],
|
|
pinfo->dimm_params[i],
|
|
dbw_capacity_adjust[i],
|
|
size_only);
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
{
|
|
/*
|
|
* Compute the amount of memory available just by
|
|
* looking for the highest valid CSn_BNDS value.
|
|
* This allows us to also experiment with using
|
|
* only CS0 when using dual-rank DIMMs.
|
|
*/
|
|
unsigned int max_end = 0;
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
|
|
fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
|
|
if (reg->cs[j].config & 0x80000000) {
|
|
unsigned int end;
|
|
/*
|
|
* 0xfffffff is a special value we put
|
|
* for unused bnds
|
|
*/
|
|
if (reg->cs[j].bnds == 0xffffffff)
|
|
continue;
|
|
end = reg->cs[j].bnds & 0xffff;
|
|
if (end > max_end) {
|
|
max_end = end;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
total_mem = 1 + (((unsigned long long)max_end << 24ULL)
|
|
| 0xFFFFFFULL);
|
|
}
|
|
|
|
return total_mem;
|
|
}
|
|
|
|
/*
|
|
* fsl_ddr_sdram() -- this is the main function to be called by
|
|
* initdram() in the board file.
|
|
*
|
|
* It returns amount of memory configured in bytes.
|
|
*/
|
|
phys_size_t fsl_ddr_sdram(void)
|
|
{
|
|
unsigned int i;
|
|
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
|
|
unsigned long long total_memory;
|
|
fsl_ddr_info_t info;
|
|
int deassert_reset;
|
|
|
|
/* Reset info structure. */
|
|
memset(&info, 0, sizeof(fsl_ddr_info_t));
|
|
|
|
/* Compute it once normally. */
|
|
#ifdef CONFIG_FSL_DDR_INTERACTIVE
|
|
if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
|
|
total_memory = fsl_ddr_interactive(&info, 0);
|
|
} else if (fsl_ddr_interactive_env_var_exists()) {
|
|
total_memory = fsl_ddr_interactive(&info, 1);
|
|
} else
|
|
#endif
|
|
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
|
|
|
|
/* setup 3-way interleaving before enabling DDRC */
|
|
if (info.memctl_opts[0].memctl_interleaving) {
|
|
switch (info.memctl_opts[0].memctl_interleaving_mode) {
|
|
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
|
case FSL_DDR_3WAY_4KB_INTERLEAVING:
|
|
case FSL_DDR_3WAY_8KB_INTERLEAVING:
|
|
fsl_ddr_set_intl3r(
|
|
info.memctl_opts[0].memctl_interleaving_mode);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Program configuration registers.
|
|
* JEDEC specs requires clocks to be stable before deasserting reset
|
|
* for RDIMMs. Clocks start after chip select is enabled and clock
|
|
* control register is set. During step 1, all controllers have their
|
|
* registers set but not enabled. Step 2 proceeds after deasserting
|
|
* reset through board FPGA or GPIO.
|
|
* For non-registered DIMMs, initialization can go through but it is
|
|
* also OK to follow the same flow.
|
|
*/
|
|
deassert_reset = board_need_mem_reset();
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
if (info.common_timing_params[i].all_DIMMs_registered)
|
|
deassert_reset = 1;
|
|
}
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
debug("Programming controller %u\n", i);
|
|
if (info.common_timing_params[i].ndimms_present == 0) {
|
|
debug("No dimms present on controller %u; "
|
|
"skipping programming\n", i);
|
|
continue;
|
|
}
|
|
/*
|
|
* The following call with step = 1 returns before enabling
|
|
* the controller. It has to finish with step = 2 later.
|
|
*/
|
|
fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
|
|
deassert_reset ? 1 : 0);
|
|
}
|
|
if (deassert_reset) {
|
|
/* Use board FPGA or GPIO to deassert reset signal */
|
|
debug("Deasserting mem reset\n");
|
|
board_deassert_mem_reset();
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
/* Call with step = 2 to continue initialization */
|
|
fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
|
|
i, 2);
|
|
}
|
|
}
|
|
|
|
/* program LAWs */
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
if (info.memctl_opts[i].memctl_interleaving) {
|
|
switch (info.memctl_opts[i].memctl_interleaving_mode) {
|
|
case FSL_DDR_CACHE_LINE_INTERLEAVING:
|
|
case FSL_DDR_PAGE_INTERLEAVING:
|
|
case FSL_DDR_BANK_INTERLEAVING:
|
|
case FSL_DDR_SUPERBANK_INTERLEAVING:
|
|
if (i == 0) {
|
|
law_memctl = LAW_TRGT_IF_DDR_INTRLV;
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
law_memctl, i);
|
|
} else if (i == 2) {
|
|
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
law_memctl, i);
|
|
}
|
|
break;
|
|
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
|
case FSL_DDR_3WAY_4KB_INTERLEAVING:
|
|
case FSL_DDR_3WAY_8KB_INTERLEAVING:
|
|
law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
|
|
if (i == 0) {
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
law_memctl, i);
|
|
}
|
|
break;
|
|
case FSL_DDR_4WAY_1KB_INTERLEAVING:
|
|
case FSL_DDR_4WAY_4KB_INTERLEAVING:
|
|
case FSL_DDR_4WAY_8KB_INTERLEAVING:
|
|
law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
|
|
if (i == 0)
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
law_memctl, i);
|
|
/* place holder for future 4-way interleaving */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else {
|
|
switch (i) {
|
|
case 0:
|
|
law_memctl = LAW_TRGT_IF_DDR_1;
|
|
break;
|
|
case 1:
|
|
law_memctl = LAW_TRGT_IF_DDR_2;
|
|
break;
|
|
case 2:
|
|
law_memctl = LAW_TRGT_IF_DDR_3;
|
|
break;
|
|
case 3:
|
|
law_memctl = LAW_TRGT_IF_DDR_4;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
law_memctl, i);
|
|
}
|
|
}
|
|
|
|
debug("total_memory by %s = %llu\n", __func__, total_memory);
|
|
|
|
#if !defined(CONFIG_PHYS_64BIT)
|
|
/* Check for 4G or more. Bad. */
|
|
if (total_memory >= (1ull << 32)) {
|
|
printf("Detected %lld MB of memory\n", total_memory >> 20);
|
|
printf(" This U-Boot only supports < 4G of DDR\n");
|
|
printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
|
|
printf(" "); /* re-align to match init_func_ram print */
|
|
total_memory = CONFIG_MAX_MEM_MAPPED;
|
|
}
|
|
#endif
|
|
|
|
return total_memory;
|
|
}
|
|
|
|
/*
|
|
* fsl_ddr_sdram_size() - This function only returns the size of the total
|
|
* memory without setting ddr control registers.
|
|
*/
|
|
phys_size_t
|
|
fsl_ddr_sdram_size(void)
|
|
{
|
|
fsl_ddr_info_t info;
|
|
unsigned long long total_memory = 0;
|
|
|
|
memset(&info, 0 , sizeof(fsl_ddr_info_t));
|
|
|
|
/* Compute it once normally. */
|
|
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
|
|
|
|
return total_memory;
|
|
}
|