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https://github.com/brain-hackers/u-boot-brain
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c4bd12a7da
For !DM case busses are listed as ZynqMP> i2c bus Bus 0: zynq_0 Bus 1: zynq_0->PCA9544A@0x75:0 Bus 2: zynq_0->PCA9544A@0x75:1 Bus 3: zynq_0->PCA9544A@0x75:2 Bus 4: zynq_1 Bus 5: zynq_1->PCA9548@0x74:0 Bus 6: zynq_1->PCA9548@0x74:1 Bus 7: zynq_1->PCA9548@0x74:2 Bus 8: zynq_1->PCA9548@0x74:3 Bus 9: zynq_1->PCA9548@0x74:4 Bus 10: zynq_1->PCA9548@0x75:0 Bus 11: zynq_1->PCA9548@0x75:1 Bus 12: zynq_1->PCA9548@0x75:2 Bus 13: zynq_1->PCA9548@0x75:3 Bus 14: zynq_1->PCA9548@0x75:4 Bus 15: zynq_1->PCA9548@0x75:5 Bus 16: zynq_1->PCA9548@0x75:6 Bus 17: zynq_1->PCA9548@0x75:7 where is exactly describing i2c bus topology. By moving to DM case i2c mux buses are using names from DT and because i2c-muxes describing sub busses with the same names like i2c@0, etc it is hard to identify which bus is where. Linux is adding topology information to i2c-mux busses to identify them better. This patch is doing the same and composing bus name with topology information. When patch is applied with topology information on zcu102-revA. ZynqMP> i2c bus Bus 0: i2c@ff020000 20: gpio@20, offset len 1, flags 0 21: gpio@21, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 2: i2c@ff020000->i2c-mux@75->i2c@0 Bus 3: i2c@ff020000->i2c-mux@75->i2c@1 Bus 4: i2c@ff020000->i2c-mux@75->i2c@2 Bus 1: i2c@ff030000 (active 1) 74: i2c-mux@74, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 5: i2c@ff030000->i2c-mux@74->i2c@0 (active 5) 54: eeprom@54, offset len 1, flags 0 Bus 6: i2c@ff030000->i2c-mux@74->i2c@1 Bus 7: i2c@ff030000->i2c-mux@74->i2c@2 Bus 8: i2c@ff030000->i2c-mux@74->i2c@3 Bus 9: i2c@ff030000->i2c-mux@74->i2c@4 Bus 10: i2c@ff030000->i2c-mux@75->i2c@0 Bus 11: i2c@ff030000->i2c-mux@75->i2c@1 Bus 12: i2c@ff030000->i2c-mux@75->i2c@2 Bus 13: i2c@ff030000->i2c-mux@75->i2c@3 Bus 14: i2c@ff030000->i2c-mux@75->i2c@4 Bus 15: i2c@ff030000->i2c-mux@75->i2c@5 Bus 16: i2c@ff030000->i2c-mux@75->i2c@6 Bus 17: i2c@ff030000->i2c-mux@75->i2c@7 Behavior before the patch is applied. ZynqMP> i2c bus Bus 0: i2c@ff020000 20: gpio@20, offset len 1, flags 0 21: gpio@21, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 2: i2c@0 Bus 3: i2c@1 Bus 4: i2c@2 Bus 1: i2c@ff030000 (active 1) 74: i2c-mux@74, offset len 1, flags 0 75: i2c-mux@75, offset len 1, flags 0 Bus 5: i2c@0 (active 5) 54: eeprom@54, offset len 1, flags 0 Bus 6: i2c@1 Bus 7: i2c@2 Bus 8: i2c@3 Bus 9: i2c@4 Bus 10: i2c@0 Bus 11: i2c@1 Bus 12: i2c@2 Bus 13: i2c@3 Bus 14: i2c@4 Bus 15: i2c@5 Bus 16: i2c@6 Bus 17: i2c@7 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> |
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|---|---|---|
| .. | ||
| muxes | ||
| ast_i2c.c | ||
| ast_i2c.h | ||
| at91_i2c.c | ||
| at91_i2c.h | ||
| cros_ec_ldo.c | ||
| cros_ec_tunnel.c | ||
| davinci_i2c.c | ||
| davinci_i2c.h | ||
| designware_i2c.c | ||
| designware_i2c.h | ||
| exynos_hs_i2c.c | ||
| fsl_i2c.c | ||
| i2c_core.c | ||
| i2c-cdns.c | ||
| i2c-emul-uclass.c | ||
| i2c-gpio.c | ||
| i2c-uclass-compat.c | ||
| i2c-uclass.c | ||
| i2c-uniphier-f.c | ||
| i2c-uniphier.c | ||
| i2c-versatile.c | ||
| ihs_i2c.c | ||
| imx_lpi2c.c | ||
| intel_i2c.c | ||
| Kconfig | ||
| kona_i2c.c | ||
| lpc32xx_i2c.c | ||
| Makefile | ||
| meson_i2c.c | ||
| mv_i2c.c | ||
| mv_i2c.h | ||
| mvtwsi.c | ||
| mxc_i2c.c | ||
| omap24xx_i2c.c | ||
| omap24xx_i2c.h | ||
| rcar_i2c.c | ||
| rcar_iic.c | ||
| rk_i2c.c | ||
| s3c24x0_i2c.c | ||
| s3c24x0_i2c.h | ||
| sandbox_i2c.c | ||
| sh_i2c.c | ||
| soft_i2c.c | ||
| stm32f7_i2c.c | ||
| tegra_i2c.c | ||
| tegra186_bpmp_i2c.c | ||
| xilinx_xiic.c | ||
| zynq_i2c.c | ||