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b87e6f88e9
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| cpu.c | ||
| cpu.h | ||
| fdt.c | ||
| lowlevel.S | ||
| Makefile | ||
| mp.c | ||
| mp.h | ||
| README | ||
| speed.c | ||
| speed.h | ||
# # Copyright 2014 Freescale Semiconductor # # SPDX-License-Identifier: GPL-2.0+ # Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A.