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armv8/fsl-lsch3: Add support for second DDR clock

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FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2015-01-06 13:18:49 -08:00
parent 49fd1f3f26
commit b87e6f88e9
4 changed files with 21 additions and 2 deletions
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1
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
View File

@ -367,6 +367,7 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
return 0;

16
arch/arm/cpu/armv8/fsl-lsch3/speed.c
View File

@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
@ -129,7 +134,7 @@ int get_clocks(void)
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
* get_ddr_freq
* return ddr bus freq in Hz
*********************************************/
ulong get_ddr_freq(ulong dummy)
ulong get_ddr_freq(ulong ctrl_num)
{
if (!gd->mem_clk)
get_clocks();
/*
* DDR controller 0 & 1 are on memory complex 0
* DDR controler 2 is on memory complext 1
*/
if (ctrl_num >= 2)
return gd->arch.mem2_clk;
return gd->mem_clk;
}

3
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
View File

@ -15,6 +15,7 @@ struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_ddrbus2;
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
@ -60,6 +61,8 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
u8 res_280[0x300-0x280];

3
arch/arm/include/asm/global_data.h
View File

@ -48,6 +48,9 @@ struct arch_global_data {
#ifdef CONFIG_OMAP
struct omap_boot_parameters omap_boot_params;
#endif
#ifdef CONFIG_FSL_LSCH3
unsigned long mem2_clk;
#endif
};
#include <asm-generic/global_data.h>