mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-16 09:43:39 +09:00
7c352cd38d
The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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*
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* Functions for omap5 based boards.
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*
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* (C) Copyright 2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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* Sricharan <r.sricharan@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <linux/sizes.h>
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#include <asm/utils.h>
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#include <asm/arch/gpio.h>
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#include <asm/emif.h>
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#include <asm/omap_common.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
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static struct gpio_bank gpio_bank_54xx[8] = {
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{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
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void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
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{
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int i;
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struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
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for (i = 0; i < size; i++, pad++)
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writel(pad->val, base + pad->offset);
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}
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#ifdef CONFIG_SPL_BUILD
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/* LPDDR2 specific IO settings */
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static void io_settings_lpddr2(void)
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{
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const struct ctrl_ioregs *ioregs;
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get_ioregs(&ioregs);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
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writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
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writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
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writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
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}
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/* DDR3 specific IO settings */
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static void io_settings_ddr3(void)
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{
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u32 io_settings = 0;
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const struct ctrl_ioregs *ioregs;
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get_ioregs(&ioregs);
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writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
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writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
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writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
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writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
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if (!is_dra7xx()) {
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writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
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}
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/* omap5432 does not use lpddr2 */
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
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writel(ioregs->ctrl_emif_sdram_config_ext,
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(*ctrl)->control_emif1_sdram_config_ext);
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if (!is_dra72x())
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writel(ioregs->ctrl_emif_sdram_config_ext,
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(*ctrl)->control_emif2_sdram_config_ext);
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if (is_omap54xx()) {
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/* Disable DLL select */
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io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
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& 0xFFEFFFFF);
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writel(io_settings,
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(*ctrl)->control_port_emif1_sdram_config);
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io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
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& 0xFFEFFFFF);
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writel(io_settings,
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(*ctrl)->control_port_emif2_sdram_config);
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} else {
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writel(ioregs->ctrl_ddr_ctrl_ext_0,
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(*ctrl)->control_ddr_control_ext_0);
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}
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}
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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void do_io_settings(void)
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{
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u32 io_settings = 0, mask = 0;
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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/* Impedance settings EMMC, C2C 1,2, hsi2 */
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mask = (ds_mask << 2) | (ds_mask << 8) |
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(ds_mask << 16) | (ds_mask << 18);
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io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
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(~mask);
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io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
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(ds_45_ohm << 18) | (ds_60_ohm << 2);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
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/* Impedance settings Mcspi2 */
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mask = (ds_mask << 30);
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io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
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(~mask);
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io_settings |= (ds_60_ohm << 30);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
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/* Impedance settings C2C 3,4 */
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mask = (ds_mask << 14) | (ds_mask << 16);
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io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
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(~mask);
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io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
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/* Slew rate settings EMMC, C2C 1,2 */
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mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
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io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
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(~mask);
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io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
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/* Slew rate settings hsi2, Mcspi2 */
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mask = (sc_mask << 24) | (sc_mask << 28);
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io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
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(~mask);
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io_settings |= (sc_fast << 28) | (sc_fast << 24);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
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/* Slew rate settings C2C 3,4 */
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mask = (sc_mask << 16) | (sc_mask << 18);
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io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
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(~mask);
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io_settings |= (sc_na << 16) | (sc_na << 18);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
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/* impedance and slew rate settings for usb */
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mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
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(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
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io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
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(~mask);
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io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
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(ds_60_ohm << 23) | (sc_fast << 20) |
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(sc_fast << 17) | (sc_fast << 14);
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writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
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if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
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io_settings_lpddr2();
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else
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io_settings_ddr3();
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}
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static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
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{0x45, 0x1}, /* 12 MHz */
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{-1, -1}, /* 13 MHz */
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{0x63, 0x2}, /* 16.8 MHz */
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{0x57, 0x2}, /* 19.2 MHz */
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{0x20, 0x1}, /* 26 MHz */
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{-1, -1}, /* 27 MHz */
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{0x41, 0x3} /* 38.4 MHz */
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};
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void srcomp_enable(void)
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{
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u32 srcomp_value, mul_factor, div_factor, clk_val, i;
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u32 sysclk_ind = get_sys_clk_index();
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u32 omap_rev = omap_revision();
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if (!is_omap54xx())
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return;
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mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
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div_factor = srcomp_parameters[sysclk_ind].divide_factor;
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for (i = 0; i < 4; i++) {
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srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value &=
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~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
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srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
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(div_factor << DIVIDE_FACTOR_XS_SHIFT);
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writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
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}
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if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
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clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
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clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
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writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
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for (i = 0; i < 4; i++) {
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srcomp_value =
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readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value &= ~PWRDWN_XS_MASK;
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writel(srcomp_value,
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(*ctrl)->control_srcomp_north_side + i*4);
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while (((readl((*ctrl)->control_srcomp_north_side + i*4)
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& SRCODE_READ_XS_MASK) >>
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SRCODE_READ_XS_SHIFT) == 0)
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;
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srcomp_value =
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readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value &= ~OVERRIDE_XS_MASK;
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writel(srcomp_value,
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(*ctrl)->control_srcomp_north_side + i*4);
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}
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} else {
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srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
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srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
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DIVIDE_FACTOR_XS_MASK);
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srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
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(div_factor << DIVIDE_FACTOR_XS_SHIFT);
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writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
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for (i = 0; i < 4; i++) {
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srcomp_value =
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readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
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writel(srcomp_value,
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(*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value =
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readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value &= ~OVERRIDE_XS_MASK;
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writel(srcomp_value,
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(*ctrl)->control_srcomp_north_side + i*4);
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}
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srcomp_value =
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readl((*ctrl)->control_srcomp_east_side_wkup);
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srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
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writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
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srcomp_value =
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readl((*ctrl)->control_srcomp_east_side_wkup);
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srcomp_value &= ~OVERRIDE_XS_MASK;
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writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
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clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
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clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
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writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
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clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
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clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
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writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
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for (i = 0; i < 4; i++) {
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while (((readl((*ctrl)->control_srcomp_north_side + i*4)
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& SRCODE_READ_XS_MASK) >>
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SRCODE_READ_XS_SHIFT) == 0)
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;
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srcomp_value =
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readl((*ctrl)->control_srcomp_north_side + i*4);
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srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
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writel(srcomp_value,
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(*ctrl)->control_srcomp_north_side + i*4);
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}
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while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
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SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
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;
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srcomp_value =
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readl((*ctrl)->control_srcomp_east_side_wkup);
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srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
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writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
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}
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}
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#endif
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void config_data_eye_leveling_samples(u32 emif_base)
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{
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const struct ctrl_ioregs *ioregs;
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get_ioregs(&ioregs);
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/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
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if (emif_base == EMIF1_BASE)
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writel(ioregs->ctrl_emif_sdram_config_ext_final,
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(*ctrl)->control_emif1_sdram_config_ext);
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else if (emif_base == EMIF2_BASE)
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writel(ioregs->ctrl_emif_sdram_config_ext_final,
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(*ctrl)->control_emif2_sdram_config_ext);
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}
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void init_cpu_configuration(void)
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{
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u32 l2actlr;
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asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
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/*
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* L2ACTLR: Ensure to enable the following:
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* 3: Disable clean/evict push to external
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* 4: Disable WriteUnique and WriteLineUnique transactions from master
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* 8: Disable DVM/CMO message broadcast
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*/
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l2actlr |= 0x118;
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omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
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}
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void init_omap_revision(void)
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{
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/*
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* For some of the ES2/ES1 boards ID_CODE is not reliable:
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* Also, ES1 and ES2 have different ARM revisions
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* So use ARM revision for identification
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*/
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unsigned int rev = cortex_rev();
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP5430_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5430_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5432_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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case OMAP5430_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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case DRA752_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = DRA752_ES1_0;
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break;
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case DRA752_CONTROL_ID_CODE_ES1_1:
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*omap_si_rev = DRA752_ES1_1;
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break;
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case DRA722_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = DRA722_ES1_0;
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break;
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default:
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*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
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}
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init_cpu_configuration();
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}
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void reset_cpu(ulong ignored)
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{
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u32 omap_rev = omap_revision();
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/*
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* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
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* So use cold reset in case instead.
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*/
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if (omap_rev == OMAP5430_ES1_0)
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writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
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else
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writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
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}
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u32 warm_reset(void)
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{
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return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
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}
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void setup_warmreset_time(void)
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{
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u32 rst_time, rst_val;
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#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
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rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
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#else
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rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
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#endif
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rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
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if (rst_time > RSTTIME1_MASK)
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rst_time = RSTTIME1_MASK;
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rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
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rst_val |= rst_time;
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writel(rst_val, (*prcm)->prm_rsttime);
|
|
}
|
|
|
|
void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
|
|
u32 cpu_rev_comb, u32 cpu_variant,
|
|
u32 cpu_rev)
|
|
{
|
|
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
|
|
}
|