u-boot-brain/arch/riscv
Bin Meng 644a3cd77e riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
..
cpu riscv: ax25: Hide the ax25-specific Kconfig option 2018-12-18 09:56:26 +08:00
dts riscv: dts: Add ae350_32.dts for RV32I 2018-11-26 13:57:55 +08:00
include/asm riscv: Add a SYSCON driver for SiFive's Core Local Interruptor 2018-12-18 09:56:26 +08:00
lib riscv: Add a SYSCON driver for SiFive's Core Local Interruptor 2018-12-18 09:56:26 +08:00
config.mk riscv: enable -fdata-sections 2018-11-26 13:57:29 +08:00
Kconfig riscv: Add a SYSCON driver for SiFive's Core Local Interruptor 2018-12-18 09:56:26 +08:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00