mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
644a3cd77e
This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
108 lines
2.0 KiB
Plaintext
108 lines
2.0 KiB
Plaintext
menu "RISC-V architecture"
|
|
depends on RISCV
|
|
|
|
config SYS_ARCH
|
|
default "riscv"
|
|
|
|
choice
|
|
prompt "Target select"
|
|
optional
|
|
|
|
config TARGET_AX25_AE350
|
|
bool "Support ax25-ae350"
|
|
|
|
config TARGET_QEMU_VIRT
|
|
bool "Support QEMU Virt Board"
|
|
|
|
endchoice
|
|
|
|
# board-specific options below
|
|
source "board/AndesTech/ax25-ae350/Kconfig"
|
|
source "board/emulation/qemu-riscv/Kconfig"
|
|
|
|
# platform-specific options below
|
|
source "arch/riscv/cpu/ax25/Kconfig"
|
|
|
|
# architecture-specific options below
|
|
|
|
choice
|
|
prompt "Base ISA"
|
|
default ARCH_RV32I
|
|
|
|
config ARCH_RV32I
|
|
bool "RV32I"
|
|
select 32BIT
|
|
help
|
|
Choose this option to target the RV32I base integer instruction set.
|
|
|
|
config ARCH_RV64I
|
|
bool "RV64I"
|
|
select 64BIT
|
|
select PHYS_64BIT
|
|
help
|
|
Choose this option to target the RV64I base integer instruction set.
|
|
|
|
endchoice
|
|
|
|
choice
|
|
prompt "Code Model"
|
|
default CMODEL_MEDLOW
|
|
|
|
config CMODEL_MEDLOW
|
|
bool "medium low code model"
|
|
help
|
|
U-Boot and its statically defined symbols must lie within a single 2 GiB
|
|
address range and must lie between absolute addresses -2 GiB and +2 GiB.
|
|
|
|
config CMODEL_MEDANY
|
|
bool "medium any code model"
|
|
help
|
|
U-Boot and its statically defined symbols must be within any single 2 GiB
|
|
address range.
|
|
|
|
endchoice
|
|
|
|
choice
|
|
prompt "Run Mode"
|
|
default RISCV_MMODE
|
|
|
|
config RISCV_MMODE
|
|
bool "Machine"
|
|
help
|
|
Choose this option to build U-Boot for RISC-V M-Mode.
|
|
|
|
config RISCV_SMODE
|
|
bool "Supervisor"
|
|
help
|
|
Choose this option to build U-Boot for RISC-V S-Mode.
|
|
|
|
endchoice
|
|
|
|
config RISCV_ISA_C
|
|
bool "Emit compressed instructions"
|
|
default y
|
|
help
|
|
Adds "C" to the ISA subsets that the toolchain is allowed to emit
|
|
when building U-Boot, which results in compressed instructions in the
|
|
U-Boot binary.
|
|
|
|
config RISCV_ISA_A
|
|
def_bool y
|
|
|
|
config 32BIT
|
|
bool
|
|
|
|
config 64BIT
|
|
bool
|
|
|
|
config SIFIVE_CLINT
|
|
bool
|
|
depends on RISCV_MMODE
|
|
select REGMAP
|
|
select SYSCON
|
|
help
|
|
The SiFive CLINT block holds memory-mapped control and status registers
|
|
associated with software and timer interrupts.
|
|
|
|
endmenu
|