brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

riscv: ax25: Hide the ax25-specific Kconfig option

Browse Source 
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Bin Meng 2018-12-12 06:12:28 -08:00 committed by Andes
parent 60262cd041
commit 44fe795c14
3 changed files with 22 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/riscv/cpu/ax25/Kconfig
View File

@ -1,7 +1,14 @@
config RISCV_NDS
bool "AndeStar V5 ISA support"
default n
bool
help
Say Y here if you plan to run U-Boot on AndeStar v5
platforms and use some specific features which are
provided by Andes Technology AndeStar V5 Families.
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
if RISCV_NDS
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
help
Provide Andes Technology AndeStar V5 families specific cache support.
endif

12
arch/riscv/cpu/ax25/cache.c
View File

@ -9,7 +9,7 @@
void icache_enable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
@ -22,7 +22,7 @@ void icache_enable(void)
void icache_disable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
@ -36,7 +36,7 @@ void icache_disable(void)
void dcache_enable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
@ -49,7 +49,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
"csrr t1, mcache_ctl\n\t"
@ -64,7 +64,7 @@ int icache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x01\n\t"
@ -81,7 +81,7 @@ int dcache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x02\n\t"

4
board/AndesTech/ax25-ae350/Kconfig
View File

@ -21,4 +21,8 @@ config ENV_SIZE
config ENV_OFFSET
default 0x140000 if ENV_IS_IN_SPI_FLASH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
endif