Stefan Roese 399b867fac mips: octeon: cache.c: Flush all pending writes in flush_dcache_range() ... As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>		2020-10-07 20:25:57 +02:00
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include	mips: octeon: Add mangle-port.h	2020-10-07 20:25:57 +02:00
cache.c	mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()	2020-10-07 20:25:57 +02:00
clock.c	mips: octeon: Initial minimal support for the Marvell Octeon SoC	2020-07-18 15:47:50 +02:00
cpu.c	mips: octeon: cpu.c: Add table for selective swapping	2020-10-07 20:25:57 +02:00
dram.c	mips: octeon: dram.c: Add RAM driver support	2020-10-07 20:25:57 +02:00
Kconfig	mips: octeon: Add minimal Octeon 3 EBB7304 EVK support	2020-07-18 15:47:50 +02:00
lowlevel_init.S	mips: octeon: use mips_mach_early_init() to copy to L2 cache	2020-07-18 15:47:50 +02:00
Makefile	mips: octeon: Initial minimal support for the Marvell Octeon SoC	2020-07-18 15:47:50 +02:00