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https://github.com/brain-hackers/u-boot-brain
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3b6bf8115f
Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| doc | ||
| cpu.c | ||
| cpu.h | ||
| fdt.c | ||
| fsl_lsch2_serdes.c | ||
| fsl_lsch2_speed.c | ||
| fsl_lsch3_serdes.c | ||
| fsl_lsch3_speed.c | ||
| Kconfig | ||
| lowlevel.S | ||
| ls1012a_serdes.c | ||
| ls1043a_psci.S | ||
| ls1043a_serdes.c | ||
| ls1046a_serdes.c | ||
| ls2080a_serdes.c | ||
| Makefile | ||
| mp.c | ||
| ppa.c | ||
| soc.c | ||
| spl.c | ||