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https://github.com/brain-hackers/u-boot-brain
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armv8: fsl_lsch2: Add LS1046A SoC support
The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -33,3 +33,7 @@ endif
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ifneq ($(CONFIG_LS1012A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
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endif
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ifneq ($(CONFIG_LS1046A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
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endif
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@ -3,6 +3,7 @@ SoC overview
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1. LS1043A
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2. LS2080A
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3. LS1012A
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4. LS1046A
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LS1043A
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---------
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@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features:
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- Two WatchDog timers
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- ARM generic timer
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- QorIQ platform's trust architecture 2.1
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LS1046A
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--------
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The LS1046A integrated multicore processor combines four ARM Cortex-A72
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1046A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A72 CPUs
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- 2 MB unified L2 Cache
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- One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Two Configurable x4 SerDes
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- Two PLLs per four-lane SerDes
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- Support for 10G operation
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- Ethernet interfaces by FMan
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- Up to 2 x XFI supporting 10G interface (MAC 9, 10)
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- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
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- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
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- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
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- Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
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- High-speed peripheral interfaces
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- Three PCIe 3.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC) supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
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case 3:
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sys_info->freq_fman[0] = freq_c_pll[0] / 3;
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break;
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case 4:
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sys_info->freq_fman[0] = freq_c_pll[0] / 4;
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break;
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case 5:
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sys_info->freq_fman[0] = sys_info->freq_systembus;
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break;
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case 6:
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sys_info->freq_fman[0] = freq_c_pll[1] / 2;
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break;
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@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
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#ifdef CONFIG_FSL_ESDHC
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#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
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sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
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switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
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case 1:
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sys_info->freq_sdhc = freq_c_pll[1];
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break;
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case 2:
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sys_info->freq_sdhc = freq_c_pll[1] / 2;
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break;
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case 3:
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sys_info->freq_sdhc = freq_c_pll[1] / 3;
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break;
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case 6:
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sys_info->freq_sdhc = freq_c_pll[0] / 2;
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break;
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default:
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printf("Error: Unknown ESDHC clock select!\n");
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break;
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}
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#else
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sys_info->freq_sdhc = sys_info->freq_systembus;
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#endif
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99
arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
Normal file
99
arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
Normal file
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@ -0,0 +1,99 @@
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_lsch2.h>
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6} },
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{0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6} },
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{0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6} },
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{0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6} },
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{0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
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{0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
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{0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
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{0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
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SGMII_FM1_DTSEC6} },
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{0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
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SGMII_FM1_DTSEC6} },
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{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
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SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
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{0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
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{0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
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{0x0506, {NONE, PCIE2, NONE, PCIE3} },
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{0x0559, {NONE, PCIE2, PCIE3, SATA1} },
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{0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
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{0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
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{}
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};
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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serdes2_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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@ -209,6 +209,33 @@
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#elif defined(CONFIG_LS1046A)
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CONFIG_SYS_FSL_DDR_BE
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_FSL_IFC_BE
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#define CONFIG_SYS_FSL_SFP_VER_3_2
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#define CONFIG_SYS_FSL_SNVS_LE
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#define CONFIG_SYS_FSL_SFP_BE
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#define CONFIG_SYS_FSL_SRK_LE
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#define CONFIG_KEY_REVOCATION
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/* SMMU Defintions */
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#define SMMU_BASE 0x09000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x01410000
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#define GICC_BASE 0x01420000
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
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CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
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CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
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CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
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CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
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CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
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CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
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};
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@ -151,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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int is_serdes_prtcl_valid(int serdes, u32 prtcl);
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#ifdef CONFIG_LS1043A
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#ifdef CONFIG_FSL_LSCH2
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const char *serdes_clock_to_string(u32 clock);
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int get_serdes_protocol(void);
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#endif
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@ -44,6 +44,8 @@ struct cpu_type {
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#define SVR_LS1012A 0x870400
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#define SVR_LS1043A 0x879200
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#define SVR_LS1023A 0x879208
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#define SVR_LS1046A 0x870700
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#define SVR_LS1026A 0x870708
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#define SVR_LS2045A 0x870120
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#define SVR_LS2080A 0x870110
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#define SVR_LS2085A 0x870100
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