Bin Meng a6d7e8c914 riscv: Split SiFive CLINT support between SPL and U-Boot proper ... At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>		2021-05-17 16:42:24 +08:00
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arch-fu540	dm: treewide: Rename ..._platdata variables to just ..._plat	2020-12-13 16:51:09 -07:00
arch-generic	dm: treewide: Rename ..._platdata variables to just ..._plat	2020-12-13 16:51:09 -07:00
asm.h	riscv: Sync csr.h with Linux kernel v5.2	2019-08-15 13:42:28 +08:00
barrier.h	riscv: make use of the barrier functions from Linux	2018-11-26 13:57:30 +08:00
bitops.h	riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()	2018-05-15 21:44:05 -04:00
byteorder.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
cache.h	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
config.h	lmb: move CONFIG_LMB in Kconfig	2021-04-22 14:09:45 -04:00
csr.h	riscv: Add option to support RISC-V privileged spec 1.9	2020-07-01 15:01:22 +08:00
dma-mapping.h	dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>	2020-02-19 21:27:30 +08:00
encoding.h	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
global_data.h	riscv: Split SiFive CLINT support between SPL and U-Boot proper	2021-05-17 16:42:24 +08:00
gpio.h	gpio: sifive: add support for DM based gpio driver for FU540-SoC	2019-10-18 09:04:01 +08:00
io.h	riscv: do not reimplement generic io functions	2018-11-26 13:57:30 +08:00
linkage.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
posix_types.h	riscv: fix use of incorrectly sized variables	2018-11-26 13:57:29 +08:00
processor.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
ptrace.h	riscv: checkpatch: Fix alignment should match open parenthesis	2018-03-30 13:13:22 +08:00
sbi.h	cmd: provide command sbi	2020-08-25 09:34:47 +08:00
sections.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
setjmp.h	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
smp.h	riscv: Use a valid bit to ignore already-pending IPIs	2020-09-30 08:54:52 +08:00
spl.h	riscv: Call spl_board_init_f() in the generic SPL board_init_f()	2020-08-14 14:38:53 +08:00
string.h	riscv: assembler versions of memcpy, memmove, memset	2021-04-08 15:37:29 +08:00
syscon.h	riscv: Rework Andes PLMT as a UCLASS_TIMER driver	2020-09-30 08:54:45 +08:00
system.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
types.h	riscv: Change phys_addr_t and phys_size_t to 64-bit	2021-02-03 03:38:41 -07:00
u-boot-riscv.h	riscv: Provide a mechanism to fix DT for reserved memory	2020-04-23 10:14:16 +08:00
u-boot.h	bdinfo: riscv: Use generic bd_info	2020-06-25 13:24:10 -04:00
unaligned.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00