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riscv: assembler versions of memcpy, memmove, memset
Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Heinrich Schuchardt
Leo Yu-Chi Liang
parent
f709a0b6f9
commit
8f0dc4cfd1
@ -271,4 +271,82 @@ config STACK_SIZE_SHIFT
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config OF_BOARD_FIXUP
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default y if OF_SEPARATE && RISCV_SMODE
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config USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy"
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default y
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for SPL"
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default y if USE_ARCH_MEMCPY
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depends on SPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for TPL"
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default y if USE_ARCH_MEMCPY
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depends on TPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove"
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default y
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for SPL"
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default y if USE_ARCH_MEMCPY
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depends on SPL
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for TPL"
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default y if USE_ARCH_MEMCPY
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depends on TPL
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset"
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default y
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for SPL"
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default y if USE_ARCH_MEMSET
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depends on SPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for TPL"
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default y if USE_ARCH_MEMSET
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depends on TPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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endmenu
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@ -19,31 +19,25 @@
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#undef __HAVE_ARCH_STRRCHR
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#undef __HAVE_ARCH_STRCHR
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#undef __HAVE_ARCH_MEMCPY
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#undef __HAVE_ARCH_MEMMOVE
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#undef __HAVE_ARCH_MEMCHR
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#undef __HAVE_ARCH_MEMZERO
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#undef __HAVE_ARCH_MEMSET
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#ifdef CONFIG_MARCO_MEMSET
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#define memset(_p, _v, _n) \
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(typeof(_p) (p) = (_p); \
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typeof(_v) (v) = (_v); \
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typeof(_n) (n) = (_n); \
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{ \
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if ((n) != 0) { \
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if (__builtin_constant_p((v)) && (v) == 0) \
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__memzero((p), (n)); \
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else \
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memset((p), (v), (n)); \
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} \
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(p); \
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})
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#define memzero(_p, _n) \
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(typeof(_p) (p) = (_p); \
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typeof(_n) (n) = (_n); \
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{ if ((n) != 0) __memzero((p), (n)); (p); })
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#undef __HAVE_ARCH_MEMCPY
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#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY)
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#define __HAVE_ARCH_MEMCPY
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#endif
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extern void *memcpy(void *, const void *, __kernel_size_t);
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#undef __HAVE_ARCH_MEMMOVE
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#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE)
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#define __HAVE_ARCH_MEMMOVE
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#endif
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extern void *memmove(void *, const void *, __kernel_size_t);
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#undef __HAVE_ARCH_MEMZERO
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#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET)
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#define __HAVE_ARCH_MEMSET
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#endif
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extern void *memset(void *, int, __kernel_size_t);
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#endif /* __ASM_RISCV_STRING_H */
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@ -36,3 +36,7 @@ CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
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extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
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extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
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extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
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108
arch/riscv/lib/memcpy.S
Normal file
108
arch/riscv/lib/memcpy.S
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@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 Regents of the University of California
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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/* void *memcpy(void *, const void *, size_t) */
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ENTRY(__memcpy)
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WEAK(memcpy)
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move t6, a0 /* Preserve return value */
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/* Defer to byte-oriented copy for small sizes */
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sltiu a3, a2, 128
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bnez a3, 4f
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/* Use word-oriented copy only if low-order bits match */
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andi a3, t6, SZREG-1
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andi a4, a1, SZREG-1
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bne a3, a4, 4f
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beqz a3, 2f /* Skip if already aligned */
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/*
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* Round to nearest double word-aligned address
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* greater than or equal to start address
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*/
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andi a3, a1, ~(SZREG-1)
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addi a3, a3, SZREG
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/* Handle initial misalignment */
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sub a4, a3, a1
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1:
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lb a5, 0(a1)
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addi a1, a1, 1
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sb a5, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 1b
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sub a2, a2, a4 /* Update count */
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2:
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andi a4, a2, ~((16*SZREG)-1)
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beqz a4, 4f
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add a3, a1, a4
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3:
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REG_L a4, 0(a1)
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REG_L a5, SZREG(a1)
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REG_L a6, 2*SZREG(a1)
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REG_L a7, 3*SZREG(a1)
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REG_L t0, 4*SZREG(a1)
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REG_L t1, 5*SZREG(a1)
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REG_L t2, 6*SZREG(a1)
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REG_L t3, 7*SZREG(a1)
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REG_L t4, 8*SZREG(a1)
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REG_L t5, 9*SZREG(a1)
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REG_S a4, 0(t6)
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REG_S a5, SZREG(t6)
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REG_S a6, 2*SZREG(t6)
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REG_S a7, 3*SZREG(t6)
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REG_S t0, 4*SZREG(t6)
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REG_S t1, 5*SZREG(t6)
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REG_S t2, 6*SZREG(t6)
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REG_S t3, 7*SZREG(t6)
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REG_S t4, 8*SZREG(t6)
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REG_S t5, 9*SZREG(t6)
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REG_L a4, 10*SZREG(a1)
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REG_L a5, 11*SZREG(a1)
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REG_L a6, 12*SZREG(a1)
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REG_L a7, 13*SZREG(a1)
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REG_L t0, 14*SZREG(a1)
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REG_L t1, 15*SZREG(a1)
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addi a1, a1, 16*SZREG
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REG_S a4, 10*SZREG(t6)
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REG_S a5, 11*SZREG(t6)
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REG_S a6, 12*SZREG(t6)
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REG_S a7, 13*SZREG(t6)
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REG_S t0, 14*SZREG(t6)
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REG_S t1, 15*SZREG(t6)
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addi t6, t6, 16*SZREG
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bltu a1, a3, 3b
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andi a2, a2, (16*SZREG)-1 /* Update count */
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4:
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/* Handle trailing misalignment */
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beqz a2, 6f
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add a3, a1, a2
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/* Use word-oriented copy if co-aligned to word boundary */
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or a5, a1, t6
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or a5, a5, a3
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andi a5, a5, 3
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bnez a5, 5f
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7:
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lw a4, 0(a1)
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addi a1, a1, 4
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sw a4, 0(t6)
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addi t6, t6, 4
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bltu a1, a3, 7b
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ret
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5:
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lb a4, 0(a1)
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addi a1, a1, 1
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sb a4, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 5b
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6:
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ret
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END(__memcpy)
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64
arch/riscv/lib/memmove.S
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64
arch/riscv/lib/memmove.S
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@ -0,0 +1,64 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/asm.h>
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ENTRY(__memmove)
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WEAK(memmove)
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move t0, a0
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move t1, a1
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beq a0, a1, exit_memcpy
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beqz a2, exit_memcpy
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srli t2, a2, 0x2
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slt t3, a0, a1
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beqz t3, do_reverse
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andi a2, a2, 0x3
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li t4, 1
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beqz t2, byte_copy
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word_copy:
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lw t3, 0(a1)
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addi t2, t2, -1
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addi a1, a1, 4
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sw t3, 0(a0)
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addi a0, a0, 4
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bnez t2, word_copy
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beqz a2, exit_memcpy
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j byte_copy
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do_reverse:
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add a0, a0, a2
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add a1, a1, a2
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andi a2, a2, 0x3
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li t4, -1
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beqz t2, reverse_byte_copy
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reverse_word_copy:
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addi a1, a1, -4
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addi t2, t2, -1
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lw t3, 0(a1)
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addi a0, a0, -4
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sw t3, 0(a0)
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bnez t2, reverse_word_copy
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beqz a2, exit_memcpy
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reverse_byte_copy:
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addi a0, a0, -1
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addi a1, a1, -1
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byte_copy:
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lb t3, 0(a1)
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addi a2, a2, -1
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sb t3, 0(a0)
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add a1, a1, t4
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add a0, a0, t4
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bnez a2, byte_copy
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exit_memcpy:
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move a0, t0
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move a1, t1
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ret
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END(__memmove)
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113
arch/riscv/lib/memset.S
Normal file
113
arch/riscv/lib/memset.S
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@ -0,0 +1,113 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 Regents of the University of California
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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/* void *memset(void *, int, size_t) */
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ENTRY(__memset)
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WEAK(memset)
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move t0, a0 /* Preserve return value */
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/* Defer to byte-oriented fill for small sizes */
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sltiu a3, a2, 16
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bnez a3, 4f
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/*
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* Round to nearest XLEN-aligned address
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* greater than or equal to start address
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*/
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addi a3, t0, SZREG-1
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andi a3, a3, ~(SZREG-1)
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beq a3, t0, 2f /* Skip if already aligned */
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/* Handle initial misalignment */
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sub a4, a3, t0
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1:
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sb a1, 0(t0)
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addi t0, t0, 1
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bltu t0, a3, 1b
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sub a2, a2, a4 /* Update count */
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2: /* Duff's device with 32 XLEN stores per iteration */
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/* Broadcast value into all bytes */
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andi a1, a1, 0xff
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slli a3, a1, 8
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or a1, a3, a1
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slli a3, a1, 16
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or a1, a3, a1
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#ifdef CONFIG_64BIT
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slli a3, a1, 32
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or a1, a3, a1
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#endif
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/* Calculate end address */
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andi a4, a2, ~(SZREG-1)
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add a3, t0, a4
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andi a4, a4, 31*SZREG /* Calculate remainder */
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beqz a4, 3f /* Shortcut if no remainder */
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neg a4, a4
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addi a4, a4, 32*SZREG /* Calculate initial offset */
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/* Adjust start address with offset */
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sub t0, t0, a4
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/* Jump into loop body */
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/* Assumes 32-bit instruction lengths */
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la a5, 3f
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#ifdef CONFIG_64BIT
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srli a4, a4, 1
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#endif
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add a5, a5, a4
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jr a5
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3:
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REG_S a1, 0(t0)
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REG_S a1, SZREG(t0)
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REG_S a1, 2*SZREG(t0)
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REG_S a1, 3*SZREG(t0)
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REG_S a1, 4*SZREG(t0)
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REG_S a1, 5*SZREG(t0)
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REG_S a1, 6*SZREG(t0)
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REG_S a1, 7*SZREG(t0)
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REG_S a1, 8*SZREG(t0)
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REG_S a1, 9*SZREG(t0)
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REG_S a1, 10*SZREG(t0)
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REG_S a1, 11*SZREG(t0)
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REG_S a1, 12*SZREG(t0)
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REG_S a1, 13*SZREG(t0)
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REG_S a1, 14*SZREG(t0)
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REG_S a1, 15*SZREG(t0)
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REG_S a1, 16*SZREG(t0)
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REG_S a1, 17*SZREG(t0)
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REG_S a1, 18*SZREG(t0)
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REG_S a1, 19*SZREG(t0)
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REG_S a1, 20*SZREG(t0)
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REG_S a1, 21*SZREG(t0)
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REG_S a1, 22*SZREG(t0)
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REG_S a1, 23*SZREG(t0)
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REG_S a1, 24*SZREG(t0)
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REG_S a1, 25*SZREG(t0)
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REG_S a1, 26*SZREG(t0)
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REG_S a1, 27*SZREG(t0)
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REG_S a1, 28*SZREG(t0)
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REG_S a1, 29*SZREG(t0)
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REG_S a1, 30*SZREG(t0)
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REG_S a1, 31*SZREG(t0)
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addi t0, t0, 32*SZREG
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bltu t0, a3, 3b
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andi a2, a2, SZREG-1 /* Update count */
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4:
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/* Handle trailing misalignment */
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beqz a2, 6f
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add a3, t0, a2
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5:
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sb a1, 0(t0)
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addi t0, t0, 1
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bltu t0, a3, 5b
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6:
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ret
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END(__memset)
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