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riscv: Sync csr.h with Linux kernel v5.2
This syncs csr.h with Linux kernel 5.2, and imports asm.h that is required by csr.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
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Bin Meng
Andes
parent
8836384c75
commit
268753f8e6
68
arch/riscv/include/asm/asm.h
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68
arch/riscv/include/asm/asm.h
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@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_ASM_H
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#define _ASM_RISCV_ASM_H
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#ifdef __ASSEMBLY__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#elif __riscv_xlen == 32
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#define __REG_SEL(a, b) __ASM_STR(b)
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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#define REG_L __REG_SEL(ld, lw)
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#define REG_S __REG_SEL(sd, sw)
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#define SZREG __REG_SEL(8, 4)
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#define LGREG __REG_SEL(3, 2)
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#if __SIZEOF_POINTER__ == 8
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .dword
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#define RISCV_SZPTR 8
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#define RISCV_LGPTR 3
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#else
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#define RISCV_PTR ".dword"
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#define RISCV_SZPTR "8"
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#define RISCV_LGPTR "3"
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#endif
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#elif __SIZEOF_POINTER__ == 4
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .word
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#define RISCV_SZPTR 4
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#define RISCV_LGPTR 2
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#else
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#define RISCV_PTR ".word"
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#define RISCV_SZPTR "4"
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#define RISCV_LGPTR "2"
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#endif
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#else
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#error "Unexpected __SIZEOF_POINTER__"
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#endif
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#if (__SIZEOF_INT__ == 4)
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#define RISCV_INT __ASM_STR(.word)
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#define RISCV_SZINT __ASM_STR(4)
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#define RISCV_LGINT __ASM_STR(2)
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#else
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#error "Unexpected __SIZEOF_INT__"
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#endif
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#if (__SIZEOF_SHORT__ == 2)
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#define RISCV_SHORT __ASM_STR(.half)
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#define RISCV_SZSHORT __ASM_STR(2)
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#define RISCV_LGSHORT __ASM_STR(1)
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#else
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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#endif /* _ASM_RISCV_ASM_H */
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*
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@ -8,13 +8,14 @@
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#ifndef _ASM_RISCV_CSR_H
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#define _ASM_RISCV_CSR_H
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#include <asm/asm.h>
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#include <linux/const.h>
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/* Status register flags */
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#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
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#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
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#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
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#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
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#define SR_FS_OFF _AC(0x00000000, UL)
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@ -35,7 +36,7 @@
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#endif
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/* SATP flags */
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#if __riscv_xlen == 32
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_MODE SATP_MODE_32
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@ -45,10 +46,18 @@
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#define SATP_MODE SATP_MODE_39
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#endif
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/* Interrupt Enable and Interrupt Pending flags */
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#define MIE_MSIE _AC(0x00000008, UL) /* Software Interrupt Enable */
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#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
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#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
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/* SCAUSE */
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#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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#define EXC_INST_MISALIGNED 0
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#define EXC_INST_ACCESS 1
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@ -60,14 +69,35 @@
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#define EXC_LOAD_PAGE_FAULT 13
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#define EXC_STORE_PAGE_FAULT 15
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#ifndef __ASSEMBLY__
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/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
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#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
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#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
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#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
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#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
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#define xcsr(csr) #csr
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -76,7 +106,7 @@
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " xcsr(csr) \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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@ -85,7 +115,7 @@
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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@ -93,7 +123,7 @@
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -102,7 +132,7 @@
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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@ -110,7 +140,7 @@
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -119,7 +149,7 @@
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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