mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
a8c97f4a00
Adjust the DDR configuration dtsi such that they only generate the DRAM configuration node, the DDR controller node is moved into the stm32mp157-u-boot.dtsi itself. This permits including multiple DDR configuration dtsi files in board DT. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
242 lines
3.8 KiB
Plaintext
242 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
/*
|
|
* Copyright : STMicroelectronics 2018
|
|
*/
|
|
#include <linux/stringify.h>
|
|
|
|
&ddr {
|
|
config-DDR_MEM_COMPATIBLE {
|
|
u-boot,dm-pre-reloc;
|
|
|
|
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
|
|
|
|
st,mem-name = DDR_MEM_NAME;
|
|
st,mem-speed = <DDR_MEM_SPEED>;
|
|
st,mem-size = <DDR_MEM_SIZE>;
|
|
|
|
st,ctl-reg = <
|
|
DDR_MSTR
|
|
DDR_MRCTRL0
|
|
DDR_MRCTRL1
|
|
DDR_DERATEEN
|
|
DDR_DERATEINT
|
|
DDR_PWRCTL
|
|
DDR_PWRTMG
|
|
DDR_HWLPCTL
|
|
DDR_RFSHCTL0
|
|
DDR_RFSHCTL3
|
|
DDR_CRCPARCTL0
|
|
DDR_ZQCTL0
|
|
DDR_DFITMG0
|
|
DDR_DFITMG1
|
|
DDR_DFILPCFG0
|
|
DDR_DFIUPD0
|
|
DDR_DFIUPD1
|
|
DDR_DFIUPD2
|
|
DDR_DFIPHYMSTR
|
|
DDR_ODTMAP
|
|
DDR_DBG0
|
|
DDR_DBG1
|
|
DDR_DBGCMD
|
|
DDR_POISONCFG
|
|
DDR_PCCFG
|
|
>;
|
|
|
|
st,ctl-timing = <
|
|
DDR_RFSHTMG
|
|
DDR_DRAMTMG0
|
|
DDR_DRAMTMG1
|
|
DDR_DRAMTMG2
|
|
DDR_DRAMTMG3
|
|
DDR_DRAMTMG4
|
|
DDR_DRAMTMG5
|
|
DDR_DRAMTMG6
|
|
DDR_DRAMTMG7
|
|
DDR_DRAMTMG8
|
|
DDR_DRAMTMG14
|
|
DDR_ODTCFG
|
|
>;
|
|
|
|
st,ctl-map = <
|
|
DDR_ADDRMAP1
|
|
DDR_ADDRMAP2
|
|
DDR_ADDRMAP3
|
|
DDR_ADDRMAP4
|
|
DDR_ADDRMAP5
|
|
DDR_ADDRMAP6
|
|
DDR_ADDRMAP9
|
|
DDR_ADDRMAP10
|
|
DDR_ADDRMAP11
|
|
>;
|
|
|
|
st,ctl-perf = <
|
|
DDR_SCHED
|
|
DDR_SCHED1
|
|
DDR_PERFHPR1
|
|
DDR_PERFLPR1
|
|
DDR_PERFWR1
|
|
DDR_PCFGR_0
|
|
DDR_PCFGW_0
|
|
DDR_PCFGQOS0_0
|
|
DDR_PCFGQOS1_0
|
|
DDR_PCFGWQOS0_0
|
|
DDR_PCFGWQOS1_0
|
|
DDR_PCFGR_1
|
|
DDR_PCFGW_1
|
|
DDR_PCFGQOS0_1
|
|
DDR_PCFGQOS1_1
|
|
DDR_PCFGWQOS0_1
|
|
DDR_PCFGWQOS1_1
|
|
>;
|
|
|
|
st,phy-reg = <
|
|
DDR_PGCR
|
|
DDR_ACIOCR
|
|
DDR_DXCCR
|
|
DDR_DSGCR
|
|
DDR_DCR
|
|
DDR_ODTCR
|
|
DDR_ZQ0CR1
|
|
DDR_DX0GCR
|
|
DDR_DX1GCR
|
|
DDR_DX2GCR
|
|
DDR_DX3GCR
|
|
>;
|
|
|
|
st,phy-timing = <
|
|
DDR_PTR0
|
|
DDR_PTR1
|
|
DDR_PTR2
|
|
DDR_DTPR0
|
|
DDR_DTPR1
|
|
DDR_DTPR2
|
|
DDR_MR0
|
|
DDR_MR1
|
|
DDR_MR2
|
|
DDR_MR3
|
|
>;
|
|
|
|
#ifdef DDR_PHY_CAL_SKIP
|
|
st,phy-cal = <
|
|
DDR_DX0DLLCR
|
|
DDR_DX0DQTR
|
|
DDR_DX0DQSTR
|
|
DDR_DX1DLLCR
|
|
DDR_DX1DQTR
|
|
DDR_DX1DQSTR
|
|
DDR_DX2DLLCR
|
|
DDR_DX2DQTR
|
|
DDR_DX2DQSTR
|
|
DDR_DX3DLLCR
|
|
DDR_DX3DQTR
|
|
DDR_DX3DQSTR
|
|
>;
|
|
|
|
#endif
|
|
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
#undef DDR_MEM_COMPATIBLE
|
|
#undef DDR_MEM_NAME
|
|
#undef DDR_MEM_SPEED
|
|
#undef DDR_MEM_SIZE
|
|
|
|
#undef DDR_MSTR
|
|
#undef DDR_MRCTRL0
|
|
#undef DDR_MRCTRL1
|
|
#undef DDR_DERATEEN
|
|
#undef DDR_DERATEINT
|
|
#undef DDR_PWRCTL
|
|
#undef DDR_PWRTMG
|
|
#undef DDR_HWLPCTL
|
|
#undef DDR_RFSHCTL0
|
|
#undef DDR_RFSHCTL3
|
|
#undef DDR_RFSHTMG
|
|
#undef DDR_CRCPARCTL0
|
|
#undef DDR_DRAMTMG0
|
|
#undef DDR_DRAMTMG1
|
|
#undef DDR_DRAMTMG2
|
|
#undef DDR_DRAMTMG3
|
|
#undef DDR_DRAMTMG4
|
|
#undef DDR_DRAMTMG5
|
|
#undef DDR_DRAMTMG6
|
|
#undef DDR_DRAMTMG7
|
|
#undef DDR_DRAMTMG8
|
|
#undef DDR_DRAMTMG14
|
|
#undef DDR_ZQCTL0
|
|
#undef DDR_DFITMG0
|
|
#undef DDR_DFITMG1
|
|
#undef DDR_DFILPCFG0
|
|
#undef DDR_DFIUPD0
|
|
#undef DDR_DFIUPD1
|
|
#undef DDR_DFIUPD2
|
|
#undef DDR_DFIPHYMSTR
|
|
#undef DDR_ADDRMAP1
|
|
#undef DDR_ADDRMAP2
|
|
#undef DDR_ADDRMAP3
|
|
#undef DDR_ADDRMAP4
|
|
#undef DDR_ADDRMAP5
|
|
#undef DDR_ADDRMAP6
|
|
#undef DDR_ADDRMAP9
|
|
#undef DDR_ADDRMAP10
|
|
#undef DDR_ADDRMAP11
|
|
#undef DDR_ODTCFG
|
|
#undef DDR_ODTMAP
|
|
#undef DDR_SCHED
|
|
#undef DDR_SCHED1
|
|
#undef DDR_PERFHPR1
|
|
#undef DDR_PERFLPR1
|
|
#undef DDR_PERFWR1
|
|
#undef DDR_DBG0
|
|
#undef DDR_DBG1
|
|
#undef DDR_DBGCMD
|
|
#undef DDR_POISONCFG
|
|
#undef DDR_PCCFG
|
|
#undef DDR_PCFGR_0
|
|
#undef DDR_PCFGW_0
|
|
#undef DDR_PCFGQOS0_0
|
|
#undef DDR_PCFGQOS1_0
|
|
#undef DDR_PCFGWQOS0_0
|
|
#undef DDR_PCFGWQOS1_0
|
|
#undef DDR_PCFGR_1
|
|
#undef DDR_PCFGW_1
|
|
#undef DDR_PCFGQOS0_1
|
|
#undef DDR_PCFGQOS1_1
|
|
#undef DDR_PCFGWQOS0_1
|
|
#undef DDR_PCFGWQOS1_1
|
|
#undef DDR_PGCR
|
|
#undef DDR_PTR0
|
|
#undef DDR_PTR1
|
|
#undef DDR_PTR2
|
|
#undef DDR_ACIOCR
|
|
#undef DDR_DXCCR
|
|
#undef DDR_DSGCR
|
|
#undef DDR_DCR
|
|
#undef DDR_DTPR0
|
|
#undef DDR_DTPR1
|
|
#undef DDR_DTPR2
|
|
#undef DDR_MR0
|
|
#undef DDR_MR1
|
|
#undef DDR_MR2
|
|
#undef DDR_MR3
|
|
#undef DDR_ODTCR
|
|
#undef DDR_ZQ0CR1
|
|
#undef DDR_DX0GCR
|
|
#undef DDR_DX0DLLCR
|
|
#undef DDR_DX0DQTR
|
|
#undef DDR_DX0DQSTR
|
|
#undef DDR_DX1GCR
|
|
#undef DDR_DX1DLLCR
|
|
#undef DDR_DX1DQTR
|
|
#undef DDR_DX1DQSTR
|
|
#undef DDR_DX2GCR
|
|
#undef DDR_DX2DLLCR
|
|
#undef DDR_DX2DQTR
|
|
#undef DDR_DX2DQSTR
|
|
#undef DDR_DX3GCR
|
|
#undef DDR_DX3DLLCR
|
|
#undef DDR_DX3DQTR
|
|
#undef DDR_DX3DQSTR
|