Commit Graph

9275 Commits

Author SHA1 Message Date
Purna Chandra Mandal
f968467785 arm: add missing writes[bwql], reads[bwql].
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-04-10 17:18:41 +02:00
Tom Rini
e16e137c37 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-04-08 19:31:06 -04:00
mario.six@gdsys.cc
5068946120 powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx
To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-08 15:42:10 -07:00
Tom Rini
43d3fb5c06 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-04-06 14:17:22 -04:00
York Sun
3c1d218a1d armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06 10:26:46 -07:00
Vincent Siles
96077896ee arm: ls102xa: Fix order of CSU indexes in ns_access.h
This patch aims to fix the order of CSU slave index for the LS1021a
board.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06 10:26:21 -07:00
Ed Swarthout
70e21b0642 armv8: LSCH2 early and final mmu needs matching NS attribute
When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different.  For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06 08:35:09 -07:00
Stefan Roese
9fc56631a4 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-04-06 15:38:56 +02:00
Tom Rini
4ed6ed3c27 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-04-04 14:34:09 -04:00
Michal Simek
a1108da731 ARM64: zynqmp: Select SYS_CONFIG_NAME via Kconfig
This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:38 +02:00
Michal Simek
a359eaa598 microblaze: Remove !OF_CONTROL code for timer and interrupt
OF_CONTROL is enabled by default that's why this is dead code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:38 +02:00
Michal Simek
9aa65cab73 microblaze: Read information about timer/interrupts from DT
Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:38 +02:00
Joe Hershberger
a509a1d402 net: gem: Allow to set the MAC from an EEPROM
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.

Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:27:54 +02:00
Stefan Roese
ebe7890321 arm: mvebu: Don't enable d-cache on A375
Armada 375 still has some problems with d-cache enabled in the ethernet
driver (mvpp2). So lets keep the d-cache disabled until this is solved.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:15 +02:00
Stefan Roese
606576d54b arm: mvebu: Add basic support for Armada 375 eval board db-88f6720
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1

Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:10 +02:00
Stefan Roese
09e89ab4af arm: mvebu: Add basic support for the Marvell Armada 375 SoC
This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:05 +02:00
Mateusz Kulikowski
626f048bbc board: Add Qualcomm Dragonboard 410C support
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC

U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:27 -04:00
Mateusz Kulikowski
085921368b arm: Add support for Qualcomm Snapdragon family
First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:26 -04:00
Mateusz Kulikowski
d33776e43d spmi: Add sandbox test driver
This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:12 -04:00
Mateusz Kulikowski
e162c6b1a7 usb: Rename ehci-fsl.h to ehci-ci.h
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:10 -04:00
Paul Kocialkowski
41582e2e77 sniper: Change vendor name from lge to lg, matching devicetree vendor prefix
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-04-01 17:18:06 -04:00
Andreas Dannenberg
f00169a915 arm: spl: Align default board_init_f comment with code
The default board_init_f() implementation performs a call to
board_init_r() as the last step of the sequence. Fix the comment
for this function to reflect the actual execution flow.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2016-04-01 17:17:57 -04:00
Stephen Warren
f031f501ef rpi: BCM2837 and Raspberry Pi 3 32-bit support
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.

>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.

The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:

    enable_uart=1

A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:42 -04:00
Stephen Warren
95a2ddaea5 ARM: bcm2835: expand Kconfig target descriptions
This adds an explanation of which Raspberry Pi models each target option
supports.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:42 -04:00
Stephen Warren
adb91ec72b ARM: bcm2835: move CONFIG_BCM283* to Kconfig
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:41 -04:00
Nishanth Menon
2283284b05 ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.

Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
  http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
  http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
  http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
  http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)

Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K    | K2L       | K2E       | K2G
-------+-----------+-----------+-----------+---------
0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
1      | C66x 1    | C66x 1    | Reserved  | ARM
2      | C66x 2    | C66x 2    | Reserved  | ICSS0
3      | C66x 3    | C66x 3    | Reserved  | ICSS1
4      | C66x 4    | Reserved  | Reserved  | NETCP
5      | C66x 5    | Reserved  | Reserved  | CPIE
6      | C66x 6    | Reserved  | Reserved  | USB
7      | C66x 7    | Reserved  | Reserved  | Reserved
8      | ARM       | ARM       | ARM       | MLB
9      | NetCP     | NetCP     | NetCP     | PMMC
10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13     | Reserved  | Reserved  | PCIe_1    | Reserved
14     | HyperLink | PCIe_1    | HyperLink | Reserved
15     | Reserved  | Reserved  | TSIP      | Reserved
-------+-----------+-----------+-----------+---------

NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.

Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).

By marking these segments as shared, we also ensure SoC wide coherency
is enabled.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:40 -04:00
Nishanth Menon
1f807a9f32 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.

As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:40 -04:00
Tom Rini
b745e82837 arm: clang: Update support slightly
- Move most of the flags required into LLVM_RELFLAGS to test at build
  time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
  box than rpi is.

Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:39 -04:00
Tom Rini
40345e9ea7 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-04-01 08:17:55 -04:00
Siarhei Siamashka
7adbd1165c sunxi: Add Pine64+ support
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.

This patch adds a defconfig and device tree chunks for it.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Siarhei Siamashka
d96ebc468d sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.

Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Alexander Graf
0ea5a04fbc sunxi: Explicitly cast u32 pointer conversions
Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Alexander Graf
8434f03576 sunxi: Depend SPL configs on SUPPORT_SPL
We currently depend SPL config options on specific machine types which doesn't
scale. Fortunately there's already a kconfig variable that tells us whether we
want to build SPL code at all, so just depend them on this.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Alexander Graf
e6e505b93c sunxi: Move cpu independent code to mach directory
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.

Move all files that are not really tied to armv7 into a new mach-sunxi
directory.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Chen-Yu Tsai
fa06f7ed11 sunxi: Enable USB nodes for H8Homlet v2
This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:25 +02:00
Chen-Yu Tsai
d02e647432 sunxi: Enable USB on Cubietruck Plus
This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:22 +02:00
Chen-Yu Tsai
b0bea66789 sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi
This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:19 +02:00
Masahiro Yamada
6797630685 cosmetic: Fix typos "privide"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
5b66006646 ARM: uniphier: rename function names ph1_* to uniphier_*
Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
a75ecfc2a6 ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
67bd9bb80f ARM: uniphier: enable eMMC on PH1-sLD3 reference board
On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
ac2a1030e3 ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
Currently, these functions assume #address-cells and #size-cells are
both one.  Fix them to support 64bit DTB.

Also, I am fixing a buffer overrun bug while I am here.  The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS.  The number of
iteration in the loop should be limited by that CONFIG.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
89d8769298 ARM: dts: uniphier: add NAND pinmux node
This will be used to set up pin-muxing for the NAND controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
f1494981ca ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20
Since no clock driver is implemented for peripherals in U-Boot yet,
this property is needed for the serial driver to set up the divisor
register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:22 +09:00
Chen-Yu Tsai
93bac95310 sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-31 17:04:08 +02:00
Chen-Yu Tsai
0c935acb9e sunxi: usb_phy: Add support for A83T USB PHYs
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-31 17:04:06 +02:00
Hans de Goede
c74384c680 sunxi: Print soc-id from sram controller for sun8i boards
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-31 14:26:52 +02:00
Hans de Goede
5f8afd704c sunxi: Add conditional magic sram poke for A33
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-31 14:26:52 +02:00
Tom Rini
080c499df6 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2016-03-29 13:33:13 -04:00
Tom Rini
0badc648dc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-03-29 12:58:45 -04:00
Stephen Warren
8f83759fac ARM: tegra210: set PLLE_PTS bit when enabling PLLE
This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-03-29 09:57:57 -07:00
Rai Harninder
ed2530d096 armv8/ls2080ardb: Enable VID support
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.

Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Qianyu Gong
2ef846e45c armv8/ls1043aqds: dts: Set SPI mode for DSPI
Clock phase and polarity for DSPI flash need to be set.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Mingkai Hu
d91721d4ac armv8: fsl-layerscape: Add LS1023A SVR
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Mingkai Hu
16cee52138 armv8: fsl-layerscape: Fix LS1043A SVR register
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Saksham Jain
4a97a0c91d armv8: fsl-lsch3: Disable SMMU during secure boot
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:22 -07:00
Saksham Jain
809d343a1a armv8: ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
bef238cb1e armv8: ls2080: Change env variable "fdt_high"
"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
3f701cc50a armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDR
To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.

For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
216e93a185 armv8: ls2080: Add bootscript header addr for secure boot
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
fcfdb6d580 armv8: ls2080rdb: ls2080qds: Add secure boot support
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Saksham Jain
fd6dbc98a7 armv8: fsl-lsch3: Add new header for secure boot
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Saksham Jain
2827d64774 armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG
Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:19 -07:00
Saksham Jain
3808190af0 armv8: ls2080: Add SFP Configs for LS2080
In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:19 -07:00
Qianyu Gong
258b8c93ec armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPI
The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-28 17:35:38 -07:00
Peng Fan
e1bed80272 dm: i2c: mxc_i2c: implement i2c_idle_bus
Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c

This patch is an implementation following linux kernel patch:
"
commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5
Author: Gao Pan <b54642@freescale.com>
Date:   Fri Oct 23 20:28:54 2015 +0800

    i2c: imx: implement bus recovery

    Implement bus recovery methods for i2c-imx so we can recover from
    situations where SCL/SDA are stuck low.

    Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
    pinctrl to gpio mode by calling pinctrl sleep set function, and then
    use GPIO to emulate the i2c protocol to send nine dummy clock to recover
    i2c device. After recovery, set i2c pinctrl to default group setting.
"

See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
   since we have pinctrl driver/driver model gpio driver. We can
   use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
   there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
   be used, so when need to use gpio function, need to do
   "pinctrl_select_state(dev, "gpio")" and after force bus idle,
   need to switch back "pinctrl_select_state(dev, "default")".

This is example about how to use the gpio force bus
idle function:
"
 &i2c1 {
 	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	status = "okay";
	[....]
 };

[.....]

	pinctrl_i2c1_gpio: i2c1grp_gpio {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
		>;
	};
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
2016-03-28 09:22:58 +02:00
Lokesh Vutla
37217f0e0a ARM: asm: types: Introduce DMA_ADDR_T_64BIT
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide.  Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.

This is inspired from the Linux kernel types implementation[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142

Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:13:03 -04:00
Vasily Khoruzhick
9cfc059853 pxa: add support for D- and I- caches
Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2016-03-27 09:13:00 -04:00
Vasily Khoruzhick
9ddde3e6ce pxa: start.S: enable SRAM clock
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2016-03-27 09:12:59 -04:00
Vasily Khoruzhick
f19eb15426 zipitz2: restore board support
zipitz2 was dropped in 49d8899ba9

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2016-03-27 09:12:55 -04:00
Alexander Merkle
cb941e8f89 Fix typo in chosen parameter of pcm052.dts
Fix typo "choosen" instead of "chosen" in pcm052.dts.
Not tested but should fix boot process and terminal output.

Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-27 09:12:22 -04:00
Alexander Merkle
2deba805ba Fix typo in chosen parameter in vf610-twr.dts
Fix typo "choosen" instead of "chosen" in vf610-twr.dts.
Fixes boot process and terminal output for Vybrid series.

Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-27 09:12:22 -04:00
Stephen Warren
2b51315894 ARM: bcm2835: fix 64-bit build warning in mbox
Fixes:
arch/arm/mach-bcm283x/mbox.c: In function ‘bcm2835_mbox_call_prop’:
arch/arm/mach-bcm283x/mbox.c:118:48: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
arch/arm/mach-bcm283x/mbox.c:126:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:20 -04:00
Stephen Warren
ed7481c7d1 ARM: bcm283x: don't always define CONFIG_BCM2835
Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836
is defined when building for that SoC. That means there isn't a single
define that means "exactly BCM2835". This will complicate future patches
where BCM2835-vs-anything-else needs to be determined simply.

Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so
future patches are simpler.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:20 -04:00
Alexander Graf
ccd9d51ede RPi: Enable caches for rpi2
Now that we have support for running with caches enabled in HYP mode,
opt in to that on the Raspberry Pi 2. This brings a significant performance
boost.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:18 -04:00
Alexander Graf
d990f5c834 arm: Add support for HYP mode and LPAE page tables
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:17 -04:00
Alexander Graf
53eb45ef40 arm64: Add 32bit arm compatible dcache definitions
We want to be able to reuse device drivers from 32bit code, so let's add
definitions for all the dcache options that 32bit code has.

While at it, fix up the DCACHE_OFF configuration. That was setting the bits
to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless
bits and make the index explicit.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:16 -04:00
Nishanth Menon
c755e67516 ARM: OMAP5/DRA7: Expose do_set_iodelay
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Nishanth Menon
ceb7d77d6f ARM: OMAP5/DRA7: Split iodelay functionality into sub steps
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolation.

While we retain the older __recalibrate_iodelay function which provides
a ready sequencing, __recalibrate_iodelay_start and
__recalibrate_iodelay_end may be alternatively used now and the callers
will be responsible for the correct sequencing of operations.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Nishanth Menon
9c90f5135e ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0
Based on data from EMIF configuration tool 1.1.1.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:14 -04:00
Nishanth Menon
3d042e468a ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0
Based on data from EMIF configuration tool 1.1.1. Expected update for
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has
been incorporated as well.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:13 -04:00
Ravi Babu
d851ad3a66 ARM: DRA72x: Add support for detection of SR2.0
Add support for detection of SR2.0 version of DRA72x family of
processors.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:12 -04:00
Nishanth Menon
705c506e4f ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function
Fix up BOOT_SET_BITFIELD to be a static inline function to be readable
with the same functionality.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:11 -04:00
Nishanth Menon
f84e8e5b29 ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline function
BOOT_READ_BITFIELD can easily be a static inline function and be a
little more readable with the same functionality.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:11 -04:00
Nishanth Menon
bc69b505f0 ARM: keystone2: Convert BOOTBITMASK to static inline function
BOOTBITMASK is almost impossible to decode, so convert it into a simpler
static line functions of equivalent solution.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:10 -04:00
Vikas Manocha
adcc90b401 stm32f746-disco: enable flash support
This patch enables embedded flash for stm32f746 discovery board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Vikas Manocha
9ecb0c416c stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Peng Fan
7abeec2234 imx: mx7d: move MX7D to Kconfig entry
If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
 will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-26 14:16:12 +01:00
Peng Fan
9131c18cfa imx: mx6sx: move MX6SX to Kconfig entry
If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-26 14:16:12 +01:00
Stefan Roese
a7f480d92d arm: mx6: Add CCV xPress board support
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:

- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB

This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-26 14:16:12 +01:00
Stefan Roese
51560f0b04 arm: mx6: Add UART8 base address for i.MX6UL
Add the base address for the i.MX6UL so that this UART can be used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-26 14:16:12 +01:00
Fabio Estevam
47173483a3 warp7: Add initial support
Add the basic support for Warp7 board.

For more information about this reference design, please visit:

https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-26 14:16:12 +01:00
Tom Rini
a6164205ee Merge git://www.denx.de/git/u-boot-marvell 2016-03-25 12:57:18 -04:00
Leonid Iziumtsev
f7440928e6 mx27: 16-bit wide watchdog registers
Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-25 14:03:28 +01:00
Marek Vasut
b10d93ee9e arm: imx6: Switch DDR3 calibration to wait_for_bit()
Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-03-25 14:01:29 +01:00
Peng Fan
d78e7f2794 imx: print ARM clock for clocks command
Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET          50 MHz

ARM          396000 kHz
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:57:19 +01:00
Peng Fan
7082d87916 imx: mx6ul configure the PMIC_STBY_REQ pin as open drain
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:56:55 +01:00
Peng Fan
e4dc3fc068 imx: mx6ul: skip setting ahb rate
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-25 13:56:40 +01:00
Ye Li
b777789ebd imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2016-03-25 13:55:54 +01:00
Stefan Roese
aea02abec5 arm: mvebu: theadorable: Add StratixV FPGA programming support
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:48:34 +01:00
Stefan Roese
84d6919118 arm: mvebu: spi.h: Add registers for direct write access
The direct write config register is needed for SPI direct write mode
configuration.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:48:07 +01:00
Stefan Roese
21324ddb8b arm: mvebu: Add some SPI CS attributes
These attribute defines may be used to map an area of memory for direct
access to the specific SPI devices. See SPI Direct Access Mode for
further information.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:47:56 +01:00
Tom Rini
b5b84be8a7 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-03-23 18:35:11 -04:00
vishnupatekar
e449e840c5 sunxi: A83T: fix 32bit overflow warning
In mctl_channel_init, (0x50<<26) which overflows 32bit.
It was supposed to be 0x50<<16,corrected now.

Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-23 22:04:13 +01:00
Hans de Goede
d75111a79b sunxi: Select CONFIG_OF_BOARD_SETUP from arch/arm/Kconfig
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost
all our defconfigs. This also fixes it missing from some recently
added defconfigs.

This commit also modifies our ft_board_setup() to not cause warnings
when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always
build it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
fc8991c61c sunxi: Fix gmac not working due to cpu_eth_init no longer being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.

This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().

The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.

Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
2016-03-23 22:04:13 +01:00
Hans de Goede
60fa63012f sunxi: Add support for USB vbus pin for USB3
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Chen-Yu Tsai
70fe24ed93 sunxi: Support SID e-fuses on A83T and H3
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-23 22:04:13 +01:00
Hans de Goede
72cd013293 sunxi: Add defconfig and dts for Orange Pi 2 SBC
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot,
4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI,
a TRRS headphone jack for stereo out and composite out, a microphone,
an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header
and a 40-pin GPIO header.

The added dts file is identical to the one submitted to the upstream
kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
d1b7407c2f sunxi: Add defconfig and dts for Dserve DSRV9703C tablet
The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD,
1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-23 22:04:13 +01:00
Hans de Goede
6b3e71a38b sunxi: Add defconfig and dts for the Polaroid MID2809PXE4 tablet
The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked
Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD,
A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
c7e2ec4279 sunxi: Add defconfig and dts for Difrence DIT4350 tablet
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD,
A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at
i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and
rtl8188etv wifi.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
84842b23b7 sunxi: Add defconfig and dts for colorfly e708 q1 tablet
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly
e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC,
1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41,
stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip.

The added dts is identical to the dts submitted to the upstream kernel,
note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the
upstream kernel as the added dts depends on these.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
1da598208d sunxi: Fix clock_twi_onoff for sun9i
Fix a copy and paste error which caused us to use the uart rather then
the twi reset bits in clock_twi_onoff for sun9i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
a93b0fe3fd sunxi: Fix clock_twi_onoff for sun8i-a83
clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
730d2f3a41 sunxi: Fix clock_twi_onoff for sun6i
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
80e5f83c0f sunxi: Sync dts files with the upstream kernel
Sync dts files with the upstream kernel including
changes queued for 4.6:

https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/dt-for-4.6

Note this adds a number of new unused board dts files. I've asked the
authors of the kernel commits adding these to submit a matching defconfig
to u-boot.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
583fede8ee sunxi: A23: Fix some revisions needing a different magic sram poke
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.

Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Masahiro Yamada
cbbc2d80fc ARM: uniphier: add NOR boot support
This allows to boot from NOR flash (or SRAM) with help of an external
loader (NOR-loader).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
d5cf32977f ARM: uniphier: support Debug UART
For ARM32 architecture, CONFIG_DEBUG_LL is available for early
low-level debugging (and actually UniPhier 32bit SoCs use it), but
ARM64 architecture does not support it.  Instead, CONFIG_DEBUG_UART
is available as an architecture-independent debug facility.

This commit supports it on all the UniPhier SoCs (including the new
ARMv8 SoCs), which is very useful for new SoC bringups.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
650aedbfc0 ARM: uniphier: add System Control register macros for ARMv8 SoCs
The System Control block moved to a completely different register
map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones.
Define register macros in a new header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:22 +09:00
Masahiro Yamada
c8cc7213a5 ARM: uniphier: add sg_set_iectrl() function
This helper function would be useful for new SoCs with per-pin
input enable controlling, such as PH1-LD20, PH1-LD11, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:21 +09:00
Masahiro Yamada
fc26b7b91d ARM: dts: uniphier: add PH1-LD11 SoC/board device tree sources
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:21 +09:00
Masahiro Yamada
7bdd155437 ARM: dts: uniphier: add PH1-LD20 SoC/board device tree sources
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:20 +09:00
Masahiro Yamada
f6c65bc2fa ARM: uniphier: enable DDR PHY parameter dump commands by default
These commands are not necessarily needed for usual operations
(they are useful in case of DDR memory trouble), but enabling them
by default would be nice in terms of the compilation test coverage.
They are small enough, so limited impact on the memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:20 +09:00
Masahiro Yamada
36223f5de8 ARM: uniphier: add work-around to support Micro Support Card v3.6.10
Due to some hardware guy's awful work, this version is not compatible
with v3.6: the logic of BIT(0) of the reset logic is inverted! (and
v3.6.10 is horribly wrong in multiple ways), but this is what we have
to solve now.

The v3.6 expects 0x0000 set to the register for reset de-assertion,
while v3.6 does 0x0001.

This commit (ab)uses another bug of v3.6.10 to work around the issue.
The UniPhier System Bus is a 16-bit bus, which this support card is
connected to.  A 32-bit write to the bus (writel() function call) is
divided into two 16-bit write transactions, with LSB the first.  What
is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N
(Jesus Christ!).

For clarification, things are like this:

    writel(0x00010000, MICRO_SUPPORT_CARD_RESET);

is done with two bus transactions as follows

    [1] write 0x0000 to address MICRO_SUPPORT_CARD
    [2] write 0x0001 to address MICRO_SUPPORT_CARD + 2

For v3.6, [1] is written to the register and [2] is correctly ignored
because there is nothing at the address MICRO_SUPPORT_CARD + 2.  This
is what we expect.

For v3.6.10, [1] is written to the reset register and then [2] is
over-written to the same register due to the bus access bug.

For the latter, it produces a glitch signal to the BIT[0], so the
device state is lost due to the reset pulse.  This solution only
works for the start-up code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:19 +09:00
Masahiro Yamada
1b1f2319ca ARM: uniphier: drop ifdef in ddrphy-regs.h
The ifdef conditionals in header files prevent us from multi-SoC
support in a single U-Boot image.  Detect SoC specific parameters
run-time rather than define them statically with an ifdef in
ddrphy-regs.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:19 +09:00
Masahiro Yamada
5d0607c58c ARM: uniphier: refactor SBC init code
There is a bunch of duplication in the System Bus Controller init
code.  Roughly, there are two types in the SBC mode:  Adress/Data
Multiplex Mode and Save Pins Mode.  Consolidate per-SoC functions
into the two, plus per-SoC optional init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:18 +09:00
Masahiro Yamada
ea65c98050 ARM: uniphier: drop PH1- prefix from CONFIG options and file names
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long.  It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family.  Also, rename files for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:42:13 +09:00
Masahiro Yamada
6063498be8 ARM: dts: uniphier: add device tree for Micro Support Card
Import uniphier-support-card.dtsi from Linux Kernel and make it
available on the UniPhier reference boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:36:55 +09:00
Vagrant Cascadian
a6f70a3d14 Fix spelling of "transferred".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:16 -04:00
Simon Glass
2b6793de25 sandbox: Avoid calling commands when not available
Don't try to run commands when not supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:10 -04:00
Simon Glass
c1352119fd arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled
Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:09 -04:00
Tom Rini
55926ddd18 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-03-22 12:14:27 -04:00
Yangbo Lu
e477f4bdd4 armv8/fsl-lsch2: fix sdhc clock frequency value
The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:14 -07:00
Pratiyush Srivastava
b2b877306c armv8: fsl-layerscape: Updating entries in Serdes Table
The serdes protocol entries in  Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Shengzhou Liu
dd8e740c78 driver/ddr/fsl: Add workaround for erratum A-009803
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
7e7e126470 pci/layerscape: add defines for LUT
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.

Add defines for the register offsets.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
029a407dae armv8: ls2080a: update stream ID partitioning info
Update comments around how stream IDs are partitioned.
Stream IDs allocated to PCI are no longer divided up by
controller, but are instead a contiguous range

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Stuart Yoder
2d97fbb4c4 armv8: ls2080a: remove obsolete stream ID partitioning support
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Alison Wang
b2f3addbb2 arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
As the compatible property values for QSPI and DSPI dts nodes
are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
need to be updated too.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:11 -07:00
Shaohui Xie
abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Prabhakar Kushwaha
2b690b9837 armv8: lsch3: Enable WUO config for RNI-20 node
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Alexander Graf
c05016ab0b arm64: Fix layerscape mmu setup
With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.

Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Stefano Babic
312a6c016a Merge branch 'next' 2016-03-20 22:04:29 +01:00
Stefan Roese
93d9fc26cb arm: socfpga: sr1500: Misc updates (SPI speed, env location)
This patch makes the following changes to the SR1500 board port:

- Update defconfig to support SPI NOR (use make savedefconfig).
- Increase SPI speed to a maximum of 100MHz for faster system
  bootup.
- Change environment location, so that its not between SPL and
  main U-Boot. This way the combined SPL / U-Boot image can
  be used for updates.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-03-20 18:01:11 +01:00
Przemyslaw Marczak
3349682c77 dts:exynos:update pinctrl size-cells and fix child regs
This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.

Tested on:
- Odroid U3
- Odroid XU3

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2016-03-17 21:27:39 -06:00
Stefan Roese
82ceba2ca2 x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
374e78efb0 x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
e5aa8a9b15 x86: Support a chained-boot development flow
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
69ca6fd850 x86: dts: Drop memory SPD compatible string
This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
147ba41d29 x86: ivybridge: Convert to use the common SDRAM code
Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
65dd1507e3 x86: Add common SDRAM-init code
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
7e4a6ae62c x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
9ab60493c9 arm: Add a 64-bit division routine to the private library
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at
present.

This comes from coreboot version 4.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:27 +08:00
Simon Glass
1cb1611fc6 x86: Add a function to set the IOAPIC ID
Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
b697b848e8 x86: broadwell: Add support for high-speed I/O lane with ME
Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
2627c7e2c1 x86: broadwell: Add support for SDRAM setup
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
71a8f2080b x86: broadwell: Add power-control support
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
e7994858ec x86: broadwell: Add reference code support
Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
08cb7420a2 x86: broadwell: Add an LPC driver
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
da3363d5d2 x86: broadwell: Add a northbridge driver
Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
d2c29d9a2c x86: broadwell: Add a SATA driver
Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
b24f5c4f27 x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
1e6f4e5886 x86: broadwell: Add a PCH driver
Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
2f3f477b77 x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
0adf8d3548 x86: Add support for running Intel reference code
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
779653b0cb x86: Drop all the old pin configuration code
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
7ac99be6e2 x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
0a10f440e3 x86: link: Add pin configuration to the device tree
At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
e77b62e290 x86: Update microcode for secondary CPUs
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
6499277827 x86: ivybridge: Show microcode version for each core
Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
6bcb675b2f x86: Record the CPU details when starting each core
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
f7d35bc148 x86: Move common MRC Kconfig options to the common file
At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
005174d661 x86: Allow I/O functions to use pointers
It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:

   struct some_regs {
      u32 ctrl;
      u32 data;
   }

   struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;

   writel(1, &reg->ctrl);
   writel(2, &reg->data);

This does not currently work with inl(), outl(), etc. Add a cast to permit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
30928c1151 x86: Add macros to clear and set I/O bits
The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.

Add some macros to provide similar features for I/O.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
b70e742d16 x86: ivybridge: Drop sandybridge_early_init()
This function was removed in the previous clean-up. Drop it from the header
file also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
8b900a4175 x86: Move Intel Management Engine code to a common place
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
2a605d4d88 x86: Rename PORT_RESET to IO_PORT_RESET
This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
50dd3da004 x86: Move common CPU code to its own place
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
8c30b57130 x86: Move common LPC code to its own place
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
bb096b9fad x86: Add the root-complex block to common intel registers
This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
06d336cca2 x86: Create a common header for Intel register access
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
9e66506d33 x86: Move microcode code to a common location
This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
1223d737a3 x86: Move cache-as-RAM code into a common location
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
342727ace6 x86: cpu: Add functions to return the family and stepping
These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
5a34957c39 x86: broadwell: Add a few microcode files
Add two microcode files for broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
d116b53f87 x86: Add comments to the SIPI vector
The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
2254e34c3f x86: Tidy up mp_init to reduce duplication
The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
fde467772b x86: Correct duplicate POST values
Two power-on-self-test values are the same. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
d6d50db8a3 x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
963a811ab4 x86: dts: link: Add board ID GPIOs
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
a86d45491e x86: dts: link: Move SPD info into the memory controller
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
e9822d44a5 x86: link: Add required GPIO properties
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
8bf08b4207 x86: Add some more common MSR indexes
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
6d24a1eebe x86: cpu: Make the vendor table const
This does not need to be modified at run-time, so make it const.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Bin Meng
3cf23719b1 x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.

As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
26f9a9b73a x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
ff94c219e9 x86: Support writing configuration tables in high area
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
ef4d0a524e x86: Simplify codes in write_tables()
Given all table write routines have the same signature, we can
simplify the codes by using a function table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00