Commit Graph

9275 Commits

Author SHA1 Message Date
Bin Meng
cea91319c2 x86: acpi: Remove acpi_create_ssdt_generator()
This acpi_create_ssdt_generator() currently does nothing.
Remove this for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
728c4afc39 x86: acpi: Reorder code in acpi_table.h
Reorder the ACPI tables appearance by following the order:
RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the
table flag defines accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
8a8c035255 x86: acpi: Various changes to acpi_table.h
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name aslc_id and aslc-revision.
- Change MCFG base address to use 32-bit value pairs (_l and _h).
- Apply ACPI_APIC_ prefix to MADT APIC type macros and make
  their names to be more readable.
- Apply __packed to struct acpi_madt_irqoverride and struct
  acpi_madt_lapic_nmi tables, as they are not naturally aligned
  by the compiler which leads to wrong sizeof(struct).
- Rename model to res1 as it is reserved after ACPI spec 1.0.
- Apply ACPI_ prefix to the PM profile macros and change them
  to enum.
- Add ospm_flags to FACS structure which is defined since ACPI 4.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
f4446629c9 x86: acpi: Remove unused codes
- Remove #include <> header files.
- Remove APM_CNT register defines, which should not be here as
  they are SMI related.
- Remove MP_IRQ_ defines as they are duplicates of the same ones
  in asm/mpspec.h.
- Remove ACTL register defines, which should not be here as they
  are chipset specific.
- Remove functional fixed hardware defines, which are not used.
- Remove dev_scope related defines, which are not used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
ce8dd77d99 x86: dts: Update to include ACTL register details
This updates all x86 boards that currently have IRQ router in the
dts files to include ACTL register details.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
d4e61f505b x86: irq: Enable SCI on IRQ9
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2016-05-23 15:18:00 +08:00
Bin Meng
07ac84eaaa x86: irq: Reserve IRQ9 for ACPI in PIC mode
Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
dca4d1a2ce x86: acpi: Fix compiler warnings in write_acpi_tables()
Fix the following two build warnings in function 'write_acpi_tables':

  warning: format '%lx' expects argument of type 'long unsigned int',
  but argument 2 has type 'u32' [-Wformat=]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
5cb0f0dc88 x86: Fix build warning in tables.c when CONFIG_SEABIOS
The following build warning is seen in tables.c:

  warning: implicit declaration of function 'memalign'

Add the missing header file to fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
b6524477df x86: Drop asm/acpi.h
Remove asm/acpi.h which is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Tom Rini
4b6e1fda10 Merge git://git.denx.de/u-boot-dm 2016-05-17 13:58:27 -04:00
Tom Rini
27bec5c127 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-05-17 12:10:35 -04:00
Simon Glass
c649e3c91c dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSI
This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Simon Glass
e54094f2f9 sandbox: Add string and 16-bit I/O functions
Add outsw() and insw() functions for sandbox, as these are needed by the IDE
code. The functions will not do anything useful if called, but allow the
code to be compiled.

Also add out16() and in16(), required by systemace.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Simon Glass
a219639d42 dm: Rename disk uclass to ahci
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Peng Fan
102412c415 dm: spi: soft_spi: switch to use linux compatible string
1. Support compatible string "spi-gpio" which is used by Linux
   Linux use different bindings, so use UBOOT_COMPAT and
   LINUX_COMPAT to differentiate them.
2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle
   no rx or no tx case.
3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Stephen Warren
54693cbdca video: tegra: refuse to bind to disabled dcs
This prevents the following boot-time message on any board where only the
first DC is in use, yet the DC's DT node is enabled:

stdio_add_devices: Video device failed (ret=-22)

(This happens on at least Harmony, Ventana, and likely any other Tegra20
board with display enabled other than Seaboard).

The Tegra DC's DT node represents a display controller. It may itself
drive an integrated RGB display output, or be used by some other display
controller such as HDMI. For this reason the DC node itself is not
enabled/disabled in DT; the DC itself is considered a shared resource, not
the final (board-specific) display output. The node should instantiate a
display output driver only if the rgb subnode is enabled. Other output
drivers are free to use the DC if they are enabled and their DT node
references the DC's DT node. Adapt the Tegra display drivers' bind()
routine to only bind to the DC's DT node if the RGB subnode is enabled.

Now that the display driver does the right thing, remove the workaround
for this issue from Seaboard's DT file.

Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
angelo@sysam.it
5044c9cc6c m68k: add malloc memory for early malloc
To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used.
So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and
call to board_init_f_mem() is added for all cpu's.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Stefan Agner
249092fa81 imx: imx-common: print i.MX 7 SoC names consistently
According to the product website, the full names are i.MX 7Solo
and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be
consistent and print the short form for both supported i.MX 7 SoCs.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-17 17:52:20 +02:00
Stefan Agner
f716bf11f3 imx: imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-05-17 17:52:20 +02:00
Stefan Agner
1fb5133395 imx: iomux-v3: fix UART input selects
Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.
2016-05-17 17:52:20 +02:00
Eric Nelson
9f623326eb imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5
This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
2016-05-17 17:52:19 +02:00
mario.six@gdsys.cc
dbc82ce31b dm: fsl_i2c: Enable DM for FSL I2C
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-05-17 08:28:55 +02:00
mario.six@gdsys.cc
ec2c81c5d4 dm: fsl_i2c: Rename I2C register structure
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-05-17 08:28:52 +02:00
Andre Przywara
1ea4fac5a3 arm/arm64: Move barrier instructions into separate header
Commit bfb33f0bc4 ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).

Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-05-12 11:13:03 -04:00
Tom Rini
15e8cb70b4 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2016-05-06 22:12:29 -04:00
Anatolij Gustschin
5289c5fa53 socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
Building without ethernet driver doesn't work. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-05-06 18:41:49 +02:00
Marek Vasut
268da813c7 ARM: socfpga: Disable USB OC protection on SoCrates
This is mandatory, otherwise the USB does not work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2016-05-06 18:41:49 +02:00
Peng Fan
ad7af5d7e4 imx6: cache: disable L2 before touching Auxiliary Control Register
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-06 10:43:39 -04:00
Russ Dill
b67d6b003c ARM: am33xx: Fix DDR initialization delays
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.

timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.

Note that this issue introduced in v2015.01 by:

b352dde "am33xx: Drop timer_init call from s_init".

Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.

Signed-off-by: Russ Dill <russ.dill@ti.com>
2016-05-06 10:10:20 -04:00
Stephen Warren
116611937f ARM: fix ifdefs in ARMv8 lowlevel_init()
Commit 724219a65f "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.

In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:

- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.

An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.

Fixes: 724219a65f ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-06 10:10:05 -04:00
Robert P. J. Day
1cc0a9f496 Fix various typos, scattered over the code.
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
2016-05-05 21:39:26 -04:00
Stephen Warren
d9b6f58efd ARM: tegra: enable GPU node by compatible value
In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.

Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.

Cc: Thierry Reding <treding@nvidia.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-04 13:31:03 -07:00
Andreas Bießmann
09c2b8f3e3 Change my mailaddress
I'll switch my mails to my own server, so drop all gmail references.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-05-02 18:37:09 -04:00
Tom Rini
f1ab00fb53 arch/arm/imx-common/Makefile: Update u-boot.uim MKIMAGEFLAGS
We need to be passing -T firmware here and aren't.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-05-02 18:37:08 -04:00
Vagrant Cascadian
b525556e63 Revert "rockchip: rk3288: correct sdram setting"
This reverts commit b5788dc0dd.

Ram size is incorrectly reported as 512MB on a firefly-rk3288 board
with 2GB of ram. Reverting this patch displays the full amount of ram.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Simon Glass <sjg@chromium.org>
2016-05-02 13:33:18 -04:00
Tom Rini
9a1f4bae0b Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-05-02 12:18:43 -04:00
Tom Rini
821c89d38c Revert "omap3: Use raw SPL by default for mmc1"
Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot.  Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.

This reverts commit 22d90d560a.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-05-02 12:14:18 -04:00
Masahiro Yamada
bef4b024e9 ARM: uniphier: move pin-mux code into pin_init function
The code in uniphier_sld3_sbc_init() is pin-muxing, so it would
be a better fit in uniphier_sld3_early_pin_init().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:13:45 +09:00
Masahiro Yamada
5eb4150e84 ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20
The System Bus is not available by default on the ROM boot mode of
PH1-LD20.  To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:18 +09:00
Masahiro Yamada
1dce5eb9de ARM: uniphier: enable Peripherl clock to use UART in SPL
This is needed to use UART on SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:17 +09:00
Masahiro Yamada
68340966e6 ARM: uniphier: fix boot mode table of PH1-LD20
PH1-LD20 does not have the dedicated boot swap select latch.
Instead, it is controlled from the boot mode select.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:11 +09:00
Hans de Goede
bfb33f0bc4 sunxi: mctl_mem_matches: Add missing memory barrier
We are running with the caches disabled when mctl_mem_matches gets called,
but the cpu's write buffer is still there and can still get in the way,
add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases, which
was resulting in:

U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiB

U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology

CPU:   Allwinner A23 (SUN8I)
DRAM:  512 MiB

Where 512 MiB is the right amount, but the DRAM controller would be
initialized for 1024 MiB.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-04-27 19:54:11 +02:00
Nishanth Menon
e52e334e5c ARM: DRA7: Add ABB setup for all domains
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:41 -04:00
Nishanth Menon
a818097a33 ARM: OMAP5: Enable ABB configuration for MM voltage domain
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:40 -04:00
Nishanth Menon
3708e78c33 ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:39 -04:00
Nishanth Menon
2d9d057be6 ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.

This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.

Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:38 -04:00
Peter Griffin
7e4902d479 ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:10:34 -04:00
Peter Griffin
cd593ed699 ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.
Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:10:34 -04:00
Peter Griffin
9122109ad7 ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.
Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:10:31 -04:00