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x86: irq: Enable SCI on IRQ9

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By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Bin Meng 2016-05-07 07:46:14 -07:00
parent 07ac84eaaa
commit d4e61f505b
3 changed files with 31 additions and 0 deletions
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22
arch/x86/cpu/irq.c
View File

@ -147,6 +147,9 @@ static int create_pirq_routing_table(struct udevice *dev)
priv->ibase &= ~0xf;
}
priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
if (!cell || len % sizeof(struct pirq_routing))
return -EINVAL;
@ -216,6 +219,22 @@ static int create_pirq_routing_table(struct udevice *dev)
return 0;
}
static void irq_enable_sci(struct udevice *dev)
{
struct irq_router *priv = dev_get_priv(dev);
if (priv->actl_8bit) {
/* Bit7 must be turned on to enable ACPI */
dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
} else {
/* Write 0 to enable SCI on IRQ9 */
if (priv->config == PIRQ_VIA_PCI)
dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
else
writel(0, priv->ibase + priv->actl_addr);
}
}
int irq_router_common_init(struct udevice *dev)
{
int ret;
@ -229,6 +248,9 @@ int irq_router_common_init(struct udevice *dev)
pirq_route_irqs(dev, pirq_routing_table->slots,
get_irq_slot_count(pirq_routing_table));
if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
irq_enable_sci(dev);
return 0;
}

4
arch/x86/include/asm/irq.h
View File

@ -34,6 +34,8 @@ enum pirq_config {
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
* @ibase: IBASE register block base address
* @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
* @actl_addr: ACTL register offset
*/
struct irq_router {
int config;
@ -41,6 +43,8 @@ struct irq_router {
u16 irq_mask;
u32 bdf;
u32 ibase;
bool actl_8bit;
int actl_addr;
};
struct pirq_routing {

5
doc/device-tree-bindings/misc/intel,irq-router.txt
View File

@ -14,6 +14,11 @@ Required properties :
"ibase": IRQ routing is in the memory-mapped IBASE register block
- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
configuration space, required only if intel,pirq-config = "ibase".
- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
be specified. The 8-bit ACTL register is seen on ICH series chipset, like
ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
in the interrupt router's PCI configuration space, or IBASE.
- intel,pirq-link : Specifies the PIRQ link information with two cells. The
first cell is the register offset that controls the first PIRQ link routing.
The second cell is the total number of PIRQ links the router supports.