Commit Graph

70310 Commits

Author SHA1 Message Date
Ovidiu Panait ce41e73523 common: board_r: Drop initr_api wrapper
Add a return value to api_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait 0154858039 common: board_r: Drop initr_jumptable wrapper
Add a return value to jumptable_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait eb2825b79d common: board_r: Drop initr_xen wrapper
Add a return value to xen_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait 42d0d4223f common: board_r: Drop initr_noncached wrapper
Add a return value to noncached_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait b9f6d0f7db common: board_r: Drop initr_pci wrapper
Add a return value to pci_init and use it directly in the post-relocation
init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait c343e8c0bf common: board_r: Drop initr_pci_ep wrapper
Add a return value to pci_ep_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:12 -05:00
Ovidiu Panait 7addd3c6df common: board_r: Drop initr_post_backlog wrapper
Add a return value to post_output_backlog and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait fb504b2c08 common: board_r: Drop initr_secondary_cpu wrapper
Add a return value to cpu_secondary_init_r and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 51c5a2c5e4 common: board_r: Drop initr_console_record wrapper
Drop initr_console_record wrapper and call console_record_init directly.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 19b18daa29 common: board_f: Use IS_ENABLED(CONFIG_OF_EMBED) in reserve_fdt, reloc_fdt
Use IS_ENABLED(CONFIG_OF_EMBED) in instead of #ifdefs in reserve_fdt,
reloc_fdt functions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 3671668676 common: board_f: Move setup_machine code to setup_bdinfo
setup_bdinfo is used to populate various bdinfo fields, so move
setup_machine code there, as all it does is setting
gd->bd->bi_arch_number.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 4b9a121fc6 common: board_f: Use IS_ENABLED(CONFIG_TIMER_EARLY) in initf_dm
Use IS_ENABLED(CONFIG_TIMER_EARLY) instead of #ifdef in initf_dm. Also,
move timer code to the main ifdef, so that ret is defined.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 8e8d45ee02 common: board_f: Drop initf_console_record wrapper
Drop initf_console_record wrapper and call console_record_init directly.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Ovidiu Panait 4e81920ba8 common: Kconfig: Introduce CONFIG_CONSOLE_RECORD_INIT_F
Currently, the following #ifdef construct is used to check whether to run
console_record_init() during pre-relocation init:
 defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)

Introduce CONFIG_CONSOLE_RECORD_INIT_F Kconfig option to get rid of the
complex ifdef check. Also, use IS_ENABLED() instead of #ifdef.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay c698b998bb log: call vsnprintf only when it is needed to emit trace
Reduce the log overhead when the traces are filtered,
by moving the vsnprintf call from _log() to log_dispatch().

This patch avoids the printf treatment when LOG features is
activated, but trace is filtered, for example when
MAX_LOG_LEVEL=8 and LOG_DEFAULT_LEVEL=6.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2021-01-15 14:36:11 -05:00
Patrick Delaunay 742346f6cc test: log: add test for console output of dropped messages
Add a new test to check the content of the dropped messages
sent to console puts function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay bf80edb91a console: allow to record console output before ready
Allow to record the console output before before U-Boot
has a console ready.

This patch allows to test the console output in sandbox test
based on console record.

It is possible because GD_FLG_RECORD and GD_FLG_SERIAL_READY
are 2 independent flags.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay 93cdb52b2a console: remove duplicated test on gd value
Reorder test on gd value and remove the duplicated test (!gd)
in putc and puts function.

This patch is a preliminary step for rework of this function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay a4918b2310 test: add test for dropped trace before log_init
Add test for dropped trace before log_init, displayed by debug uart.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay dd500134a4 log: use console puts to output trace before LOG init
Use the console puts functions to output the traces before
the log initialization (when CONFIG_LOG is not activated).

This patch allows to display the first U-Boot traces
(with macro debug) when CONFIG_DEBUG_UART is activated
and not only drop them.

For example for traces in board_f.c requested by the macro debug,
when LOG_DEBUG is defined and CONFIG_LOG is activated.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2021-01-15 14:36:11 -05:00
Patrick Delaunay ce9af2a6b5 test: log: add test for dropped messages
Add a new test to check the dropped messages when LOG is not ready
with log_drop_count and the result of _log().

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:11 -05:00
Patrick Delaunay f0e90e0ead log: don't build the trace buffer when log is not ready
Update _log function to drop any traces when log is yet initialized:
vsnprintf is no more executed in this case.

This patch allows to reduce the cost for the dropped early debug trace.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2021-01-15 14:36:11 -05:00
Patrick Delaunay 6278ec1919 test: add LOGL_FORCE_DEBUG flags support in log tests
Add a check of the _log function with LOGL_FORCE_DEBUG flags,
used to force the trace display.

The trace should be displayed for all the level when flags
have LOGL_FORCE_DEBUG bit is set, for any filter.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15 14:36:10 -05:00
Dario Binacchi b0db69b4e1 dm: fix build errors generated by last merges
Something was wrong in the merge process into the mainline.
Some added patches access driver structure fields and functions that
have been modified by previous patches.
The patch renames:
 - dev_get_platdata to dev_get_plat
 - dev_get_uclass_platdata to dev_get_uclass_plat
 - ofdata_to_platdata to of_to_plat
 - plat_data_alloc_size to plat_auto
 - priv_auto_alloc_size to priv_auto
 - video_uc_platdata to video_uc_plat

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-15 13:12:38 -05:00
Tom Rini 83e13c3469 Merge branch '2021.04-rc' of https://github.com/lftan/u-boot
- Add ATF flow for SoC64 devices
- Update socfpgaimage to support print header and update padding flow
2021-01-15 07:55:11 -05:00
Ley Foon Tan 40551cf99c tools: socfpgaimage: update padding flow
The existing socfpgaimage always pads the image to the maximum size of
OCRAM size. This will break in the encryption flow where it expects the
image to be un-padded. The encryption tool will do the encryption for
the whole image and append the signature key at end of the image.
The signature key will append to beyond the size of OCRAM if the image
is padded with the maximum size before encryption.

Move the padding step from socfpgaimage to Makefile and pads with objcopy
command.

socfpgaimage will pad the image with 16 bytes aligned (including CRC word),
this is a requirement in encryption flow.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15 17:48:39 +08:00
Ley Foon Tan 53b59290c5 configs: socfpga: Add CONFIG_SPL_PAD_TO
Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to
size of OCRAM.

This is preparation for image padding change in socfpgaimage.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15 17:48:39 +08:00
Ley Foon Tan bcf33fac64 tools: socfpgaimage: Print image header information
Print image header information if the header is verified.

Example output from mkimage "-l" option:

$ ./tools/mkimage -l spl/u-boot-spl.sfp
Image Type      : Cyclone V / Arria V SoC Image
Validation word : 0x31305341
Version         : 0x00000000
Flags           : 0x00000000
Program length  : 0x00003a59
Header checksum : 0x00000188

$ ./tools/mkimage -l spl/u-boot-spl.sfp
Image Type      : Arria 10 SoC Image
Validation word : 0x31305341
Version         : 0x00000001
Flags           : 0x00000000
Header length   : 0x00000014
Program length  : 0x000138e0
Program entry   : 0x00000014
Header checksum : 0x00000237

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15 17:48:39 +08:00
Chee Hong Ang 7d8890d8fb configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Booting Agilex and Stratix 10 with ATF support.

SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:

SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)

U-Boot proper now starts at 0x200000 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:39 +08:00
Siew Chin Lim 362787eb57 arm: socfpga: soc64: Enable FIT image generation using binman
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to
generate FIT images.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:38 +08:00
Siew Chin Lim c87496add0 arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).

u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.

kernel.itb contains Linux Image and Linux device tree.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang 7cfb5d85ce arm: socfpga: soc64: Skip handoff data access in SSBL
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang 482bc18d4a arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang 3b07cec93a arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:38 +08:00
Chee Hong Ang 677b420a15 arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:37 +08:00
Chee Hong Ang 018d27f251 arm: socfpga: soc64: Add ATF support for Reset Manager driver
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:37 +08:00
Chee Hong Ang a90ae0167b net: designware: socfpga: Add ATF support for MAC driver
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:37 +08:00
Chee Hong Ang 6b38cc2f2b mmc: dwmmc: socfpga: Add ATF support for MMC driver
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:37 +08:00
Siew Chin Lim d456dfbaa0 mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a
status.

This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.

When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:36 +08:00
Siew Chin Lim 2e54a1d46c arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15 17:48:36 +08:00
Chee Hong Ang 313de73352 arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:36 +08:00
Chee Hong Ang 0eebfab3fe arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.

smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:36 +08:00
Chee Hong Ang dbdc1df877 arm: socfpga: Disable "spin-table" method for booting Linux
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:35 +08:00
Chee Hong Ang ac0c1fda90 arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:35 +08:00
Chee Hong Ang 200846f008 arm: socfpga: soc64: Load FIT image with ATF support
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.

For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15 17:48:35 +08:00
Chee Hong Ang acabb2acb0 arm: socfpga: Add function for checking description from FIT image
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15 17:48:34 +08:00
Tom Rini 35772ff4f6 Pull request for UEFI sub-system for efi-2021-04-rc1
In the UEFI sub-system:
 
 * implement non-blocking file services
 * print boot device and file path in helloworld.efi
 * improve detection of boot device
 * correct argument handling in efivar.py
 * implement EFI_DT_FIXUP_PROTOCOL
 
 Bug fixes:
 
 * adjust conitrace command for low baud rates
 * check that FIT images are valid FDTs
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Merge tag 'efi-2021-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-04-rc1

In the UEFI sub-system:

* implement non-blocking file services
* print boot device and file path in helloworld.efi
* improve detection of boot device
* correct argument handling in efivar.py
* implement EFI_DT_FIXUP_PROTOCOL

Bug fixes:

* adjust conitrace command for low baud rates
* check that FIT images are valid FDTs
2021-01-14 08:50:23 -05:00
Tom Rini ab1a425524 - Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
 - Activate OF_LIVE for ST stm32mp15 boards
 - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
 - Correction in stm32prog command on uart: always flush DFU on start command
 - Update USB-C power detection algorithm on DK boards
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Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
2021-01-13 15:00:53 -05:00
Tom Rini 795f8fd0b5 - sync amlogic GX & AXG DT to Linux 5.10
- Add new MESON_EE driver support for GXBB & AXG
 - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards
 - add driver for TDO tl070wsh30 panel driver
 - meson: isolate loading of socinfo
 - Add soc_rev to environment
 - Enable G12A support for saradc
 - Add correct mmcdev on VIM3(L) & Odroid-N2(C4)
 - Read MAC from fuses for VIM3 & VIM3L boards
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Merge tag 'u-boot-amlogic-20210112' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- sync amlogic GX & AXG DT to Linux 5.10
- Add new MESON_EE driver support for GXBB & AXG
- Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards
- add driver for TDO tl070wsh30 panel driver
- meson: isolate loading of socinfo
- Add soc_rev to environment
- Enable G12A support for saradc
- Add correct mmcdev on VIM3(L) & Odroid-N2(C4)
- Read MAC from fuses for VIM3 & VIM3L boards
2021-01-13 07:32:02 -05:00
Patrice Chotard 7ccaa31380 MAINTAINERS: Update STi and STM32 maintainers emails in remaining files
A previous series already update STMicroelectronics emails maintainers
but some files have been omitted (Makefile, .dts, .dtsi and .rst files).
Update Patrick and my email address with the one dedicated to upstream
activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-13 09:52:58 +01:00