arm: socfpga: Add secure register access helper functions for SoC 64bits
These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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@ -73,6 +73,7 @@ obj-y += firewall.o
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obj-y += spl_agilex.o
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endif
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else
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obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
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obj-$(CONFIG_SPL_ATF) += smc_api.o
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endif
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _SECURE_REG_HELPER_H_
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#define _SECURE_REG_HELPER_H_
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#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
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#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
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#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
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#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
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int socfpga_secure_reg_read32(u32 id, u32 *val);
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int socfpga_secure_reg_write32(u32 id, u32 val);
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int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
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#endif /* _SECURE_REG_HELPER_H_ */
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@ -0,0 +1,89 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <hang.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/secure_reg_helper.h>
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#include <asm/arch/smc_api.h>
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#include <asm/arch/system_manager.h>
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#include <linux/errno.h>
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#include <linux/intel-smc.h>
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int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
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{
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switch (id) {
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case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
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*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
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break;
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case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
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*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
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break;
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case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
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*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
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break;
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case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
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*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
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break;
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default:
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return -EADDRNOTAVAIL;
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}
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return 0;
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}
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int socfpga_secure_reg_read32(u32 id, u32 *val)
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{
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int ret;
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u64 ret_arg;
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u64 args[1];
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phys_addr_t reg_addr;
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ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
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if (ret)
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return ret;
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args[0] = (u64)reg_addr;
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ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
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if (ret)
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return ret;
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*val = (u32)ret_arg;
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return 0;
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}
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int socfpga_secure_reg_write32(u32 id, u32 val)
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{
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int ret;
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u64 args[2];
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phys_addr_t reg_addr;
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ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
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if (ret)
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return ret;
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args[0] = (u64)reg_addr;
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args[1] = val;
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return invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
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}
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int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
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{
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int ret;
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u64 args[3];
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phys_addr_t reg_addr;
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ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr);
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if (ret)
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return ret;
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args[0] = (u64)reg_addr;
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args[1] = mask;
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args[2] = val;
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return invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
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}
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