Commit Graph

51947 Commits

Author SHA1 Message Date
Adam Ford
cc3fedb204 Convert CONFIG_TWL4030_LED et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TWL4030_LED
   CONFIG_TWL4030_INPUT

This also removes dead references to:
   CONFIG_TWL4030_KEYPAD

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-08-17 13:04:00 -04:00
Adam Ford
244eaea60b Convert CONFIG_VIDEO_OMAP3 to Kconfig
This converts the following to Kconfig:
   CONFIG_VIDEO_OMAP3

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-08-17 13:04:00 -04:00
Adam Ford
8ccf98b1cf Convert CONFIG_MISC_INIT_R to Kconfig
This converts the following to Kconfig:
   CONFIG_MISC_INIT_R

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Update the defaults logic slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-17 13:04:00 -04:00
Alex Kiernan
ca0d535edc Migrate bootlimit to Kconfig
Migrate boards which set bootlimit in the environment to Kconfig.

We exclude gurnard_defconfig which includes a bootlimit=, but doesn't set
CONFIG_BOOTCOUNT_LIMIT, so we'd fail to include a bootlimit setting
if we migrated it.

display5_defconfig and display5_factory_defconfig share a SYS_CONFIG_NAME,
but only display5_defconfig enables CONFIG_BOOTCOUNT_LIMIT, so we fail to
set bootlimit= in display5_factory_defconfig. This is okay because the
display5_factory_defconfig doesn't need to have it set, as it is only
meant to prepare the board in the factory.

Environment changes for all modified configs as seen from buildman:

  boards.cfg is up to date. Nothing to do.
  Summary of 3 commits for 32 boards (8 threads, 1 job per thread)
  01: Merge git://git.denx.de/u-boot-x86
         arm:  +   draco etamin rastaban pxm2 display5 thuban rut
  02: Add BOOTCOUNT_BOOTLIMIT to set reboot limit
  03: Migrate bootlimit to Kconfig
     - display5_factory: bootlimit=3

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2018-08-17 13:03:59 -04:00
Alex Kiernan
c9ad6bc235 Add BOOTCOUNT_BOOTLIMIT to set reboot limit
Add ability to set environment bootlimit from Kconfig

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-08-17 13:03:59 -04:00
Adam Ford
d7869b2183 Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17 13:03:54 -04:00
Michal Simek
4adc6605a9 dts: Fix typo in OF_LIVE Kconfig help
Fix typo in Kconfig description.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-17 09:22:35 -04:00
Simon Goldschmidt
004167048d kconfig: fix typo 'parition'
Replaced misspelled words "parition"/"paritioning" (missing 't') in two
Kconfig files by correct words "partition"/"partitioning"

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-08-17 09:22:35 -04:00
Tom Rini
8297e648b8 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-08-17 07:25:04 -04:00
Tom Rini
719afeb0b3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-17 07:24:34 -04:00
Tom Rini
86cf1c8285 configs: Migrate CONFIG_NR_DRAM_BANKS
We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
  CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
  2), set this to 8.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Ramon Fried
999a772d9f Kconfig: Migrate CONFIG_NR_DRAM_BANKS
Move CONFIG_NR_DRAM_BANKS from headers to Kconfig.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-16 16:45:02 -04:00
Ramon Fried
6b6f216f92 fdt_support: Use CONFIG_NR_DRAM_BANKS if necessary
If CONFIG_NR_DRAM_BANKS is bigger than the default
value (4) define MEMORY_BANKS_MAX as CONFIG_NR_DRAM_BANKS.

Fixes: 2a1f4f1758 ("Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if defined"")
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-16 16:45:02 -04:00
Tom Rini
0bdea7c430 CONFIG_SYS_GENERIC_BOARD: Finish migration
While we have long since migrated to CONFIG_SYS_GENERIC_BOARD being
enabled, we had just a few places left that still referenced or defined
it.  Update.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Ley Foon Tan
b0c0a715f9 arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-15 12:41:09 +02:00
Marek Vasut
4f10989280 ARM: rmobile: Enable USB PHY on Gen2
Enable support for USB PHY on the R-Car Gen2. This allows for both
of the USB host ports to be used on such boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-08-14 11:31:25 +02:00
Marek Vasut
664258887d phy: rcar: Add R-Car Gen2 PHY driver
Add a PHY driver for the R-Car Gen2 which allows configuring the mux
connected to the EHCI controllers and USBHS controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-08-14 11:31:19 +02:00
Marek Vasut
5e50adf667 phy: Fix off-by-one error when parsing DT PHY bindings
The code fails to copy the last PHY phandle argument, so it is
missing from the adjusted phandle args and the consumer cannot
use it to determine what the PHY should do.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2018-08-14 11:31:19 +02:00
Tom Rini
92e738f555 Prepare v2018.09-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-13 21:20:57 -04:00
Tom Rini
323ba02d42 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-13 20:05:58 -04:00
Marek Vasut
d81b5da3fe ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
12ea13ad43 mmc: socfpga: Add clock framework support
Add support for fetching the clock frequency both using the legacy
method in case clock framework is disabled as well as via the clock
framework if it is enabled. This allows for migration to the clock
framework on platforms which supports it while not breaking legacy
platforms. That said, the legacy method must be removed eventually.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f9f016adcd clk: socfpga: Add initial Arria10 clock driver
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
ccc97432ad ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f4c3e0dcf5 ARM: socfpga: clk: Drop unused variables on Arria10
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
49e508e962 ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
934aec71d6 ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
2af5d51cc2 ARM: socfpga: Enable DM ethernet on A10
Enable DM ethernet framework on Arria10, so that the designware GMAC
can be probed from DT as it should be.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
d6a61da462 ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
6385a8a964 ARM: socfpga: Zap unused reset code
Remove code from the reset manager that is never called.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
215a06565a net: designware: socfpga: Add Arria10 extras
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f9edeb32a9 ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13 22:35:40 +02:00
Marek Vasut
fe88c2fea7 ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
8145c1c299 ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
c29508045f ARM: dts: socfpga: Add i2c alias to A10 SoCDK
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
3d8685f155 ARM: dts: socfpga: Add missing I2C resets
The I2Cx resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
da61e50fc4 ARM: dts: socfpga: Fix Arria10 GMAC resets
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs
to work and add GMAC2 reset and OCP resets which were missing altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
f5775e69cc ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
6f96ed7e20 ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
af74658e04 ARM: socfpga: Register the FPGA on A10 in SPL again
The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Fixes: c859f2a77d ("arm: socfpga: Restructure the SPL file")
2018-08-13 22:35:16 +02:00
Simon Goldschmidt
e4ff8420c5 arm: socfpga: gen5: combine some init code for SPL and U-Boot
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Simon Goldschmidt
79a436d568 arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Patrice Chotard
f65b82ffbe MAINTAINERS: Update STM32MP fragments
Add new drivers
Add Christophe Kerello and myself as maintainers

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrick Delaunay
2deaf5cc63 ARM: dts: stm32f4: Fix DT dtc warnings
This patch fix the following warnings for for stm32f429
evaluation and discovery boards:

unnecessary #address-cells/#size-cells without "ranges" or
child "reg" property

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
638ee5af6b ARM: dts: stm32mp157: Add ADC DT node
Add ADC device tree node. This allows to get analog conversions on
stm32mp157.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
6effb56fbc ARM: dts: stm32: remove cd-inverted for stm32f746-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
4c55c83989 ARM: dts: stm32: remove cd-inverted for stm32f769-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Derald D. Woods
fe50a13b2f ARM: omap3: evm: Enable CONFIG_BLK and misc. cleanup
This commit enables CONFIG_BLK and removes USB_STORAGE which is awaiting
proper implementation for current U-Boot interfaces. Additionally the
console selection is now handled by Kconfig and no longer needs to be in
the config header. CONFIG_SYS_MALLOC_F_LEN=0x2000 was added to sync with
other boards. CONFIG_SPL_BLK and CONFIG_SPL_DM_MMC are disabled because
they currently do not allow the OMAP3-EVM (OMAP34XX) to actually boot.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2018-08-13 14:04:04 -04:00
Miquel Raynal
46703cd9f3 tpm: sandbox: fix wrong assignment with a simplification
The recv variable in sandbox_tpm2_fill_buf() is a pointer on a pointer
of a char array. It means accessing *recv is the char array pointer
itself while **recv is the first character of that array. There is no
need for such indirection here, so simplify the code.

Simplifying things will make the last assignment right: "*recv = NULL"
is now correct. The issue has been found by the following Coverity
Scan report:

    CID 183371:  Incorrect expression  (UNUSED_VALUE)
    Assigning value "4UL" to "*recv" here, but that stored value is overwritten before it can be used.
    232             *recv += sizeof(rc);
    233
    234             /* Add trailing \0 */
    235             *recv = NULL;

While at simplifying things, use '\0' instead of NULL when adding an
empty char at the end of the buffer.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-13 14:04:04 -04:00
Miquel Raynal
fd973ca696 tpm: sandbox: fix wrong check on pcr_map
The second check on pcr_map in sandbox_tpm2_xfer() is wrong. It should
check for pcr_map not being empty. Instead, it is a pure copy/paste of
the first check which is redundant.

This has been found thanks to a Coverity Scan report:

    CID 183370:  Memory - illegal accesses  (UNINIT)
    Using uninitialized value "pcr_index".
        put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv);

This is because pcr_index is initialized only if the user input is
correct, ie. at least one valid bit is set in pcr_map.

Fix the second check and also initialize pcr_index to 0 (which is
harmless in case of error) to make Coverity Scan happy.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-13 14:04:04 -04:00