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ARM: socfpga: Zap all the UART handling complexity

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The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Marek Vasut 2018-04-15 16:29:12 +02:00
parent fe88c2fea7
commit f9edeb32a9
5 changed files with 0 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-socfpga/include/mach/misc.h
View File

@ -21,12 +21,6 @@ void socfpga_fpga_add(void);
static inline void socfpga_fpga_add(void) {}
#endif
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
unsigned int dedicated_uart_com_port(const void *blob);
unsigned int shared_uart_com_port(const void *blob);
unsigned int uart_com_port(const void *blob);
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
void socfpga_sdram_remap_zero(void);
#endif

1
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
View File

@ -15,7 +15,6 @@ void socfpga_emac_manage_reset(ulong emacbase, u32 state);
int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
void socfpga_reset_uart(int assert);
int socfpga_bridges_reset(void);
struct socfpga_reset_manager {

127
arch/arm/mach-socfpga/misc_arria10.c
View File

@ -127,133 +127,6 @@ int arch_early_init_r(void)
}
#endif
/*
* This function looking the 1st encounter UART peripheral,
* and then return its offset of the dedicated/shared IO pin
* mux. offset value (zero and above).
*/
static int find_peripheral_uart(const void *blob,
int child, const char *node_name)
{
int len;
fdt_addr_t base_addr = 0;
fdt_size_t size;
const u32 *cell;
u32 value, offset = 0;
base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
if (base_addr != FDT_ADDR_T_NONE) {
cell = fdt_getprop(blob, child, "pinctrl-single,pins",
&len);
if (cell != NULL) {
for (; len > 0; len -= (2 * sizeof(u32))) {
offset = fdt32_to_cpu(*cell++);
value = fdt32_to_cpu(*cell++);
/* Found UART peripheral. */
if (value == PINMUX_UART)
return offset;
}
}
}
return -EINVAL;
}
/*
* This function looks up the 1st encounter UART peripheral,
* and then return its offset of the dedicated/shared IO pin
* mux. UART peripheral is found if the offset is not in negative
* value.
*/
static int is_peripheral_uart_true(const void *blob,
int node, const char *child_name)
{
int child, len;
const char *node_name;
child = fdt_first_subnode(blob, node);
if (child < 0)
return -EINVAL;
node_name = fdt_get_name(blob, child, &len);
while (node_name) {
if (!strcmp(child_name, node_name))
return find_peripheral_uart(blob, child, node_name);
child = fdt_next_subnode(blob, child);
if (child < 0)
break;
node_name = fdt_get_name(blob, child, &len);
}
return -1;
}
/*
* This function looking the 1st encounter UART dedicated IO peripheral,
* and then return based address of the 1st encounter UART dedicated
* IO peripheral.
*/
unsigned int dedicated_uart_com_port(const void *blob)
{
int node;
node = fdtdec_next_compatible(blob, 0,
COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
if (node < 0)
return 0;
if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
return SOCFPGA_UART1_ADDRESS;
return 0;
}
/*
* This function looking the 1st encounter UART shared IO peripheral, and then
* return based address of the 1st encounter UART shared IO peripheral.
*/
unsigned int shared_uart_com_port(const void *blob)
{
int node, ret;
node = fdtdec_next_compatible(blob, 0,
COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
if (node < 0)
return 0;
ret = is_peripheral_uart_true(blob, node, "shared");
if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 ||
ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 ||
ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3)
return SOCFPGA_UART0_ADDRESS;
else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 ||
ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 ||
ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3)
return SOCFPGA_UART1_ADDRESS;
return 0;
}
/*
* This function looking the 1st encounter UART peripheral, and then return
* base address of the 1st encounter UART peripheral.
*/
unsigned int uart_com_port(const void *blob)
{
unsigned int ret;
ret = dedicated_uart_com_port(blob);
if (ret)
return ret;
return shared_uart_com_port(blob);
}
/*
* Print CPU information
*/

12
arch/arm/mach-socfpga/reset_manager_arria10.c
View File

@ -27,18 +27,6 @@ static const struct socfpga_system_manager *sysmgr_regs =
ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
void socfpga_reset_uart(int assert)
{
unsigned int com_port;
com_port = uart_com_port(gd->fdt_blob);
if (com_port == SOCFPGA_UART1_ADDRESS)
socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
else if (com_port == SOCFPGA_UART0_ADDRESS)
socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
}
static const u32 per0fpgamasks[] = {
ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,

3
arch/arm/mach-socfpga/spl_a10.c
View File

@ -75,9 +75,6 @@ void spl_board_init(void)
config_dedicated_pins(gd->fdt_blob);
WATCHDOG_RESET();
/* Release UART from reset */
socfpga_reset_uart(0);
/* enable console uart printing */
preloader_console_init();