This patch adds support for using some GPIOs that are connected to the
I2C bus to force the bus lines state and perform some bus deblocking
sequences.
The KM common deblocking algorithm from board/keymile/common/common.c is
used. The GPIO lines used for deblocking the I2C bus are some external
GPIOs provided by the QRIO CPLD:
- SCL = GPIOA_20
- SDA = GPIOA_21
The QRIO GPIOs act in an open-drain-like manner, for 0 the line is
driven low and for 1 the GPIO is set as input and the line gets
pulled-up.
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Make use of the QRIO1 32bit register at 0x20 as bootcounter register
Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI
T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5
1 SGMII on DTSEC3
T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
Add usb2 node entry to hwconfig default
Remove DDR controller interleaving from hwconfig
Move SPI related macros out of "#ifdef CONFIG_SPIFLASH"
Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Fix commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
Add usb2 node entry in "hwconfig string"
Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller
SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code
Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- "params.bin mmc 0x38 0x8"
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin <env_text_file>
Every new env variable in text file should start with a new line.
Sample env text file:
- board/samsung/common/dfu_sample_env.txt
Requirements:
- file name: "params.bin"
- file size: 4096 Bytes - the same as CONFIG_ENV_SIZE.
Other size will cause CRC miscalculation at boot.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
CC: Piotr Wilczek <p.wilczek@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Changes:
- check image bpp instead of resolution when returns logo address
- remove 32bpp logo
- add 16bpp logo in two formats: bmp and gzipped bmp
- init logo address with "0" for unsupported bpp mode
- update boards configs with proper image size for gunzip
- extend structure vidinfo by two fields: logo_x_offset and logo_y_offset.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.
Gpio coding mask:
0x000000ff - pin number
0x00ffff00 - bank offset
0xff000000 - part number
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Enable CONFIG_REGEX on M53EVK to allow usage of regular expressions
on environment variables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The name the Linux kernel expects is 'mxc_nand' , not 'mxc-nand' .
This patch renames the driver name.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
We do not have to define CONFIG_MPC5xxx in board config headers
(and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk
because all target boards with mpc86xx cpu define it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We do not have to define CONFIG_MPC824X in board config headers
because it is defined in arch/powerpc/cpu/mpc824x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We do not have to define CONFIG_MPC512X in board config headers
because it is defined in arch/powerpc/cpu/mpc512x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We do not have to define CONFIG_MPC83xx in board config headers
because it is defined in arch/powerpc/cpu/mpc83xx/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We do not have to define CONFIG_4xx in board config headers
because it is defined in arch/powerpc/cpu/ppc4xx/config.mk.
include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx".
I believe it is a typo because "CONFIG_4x" is not used at all
in other files.
So, I also deleted "CONFIG_4x" in include/configs/JSE.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Like other architectures, CONFIG_AVR32 can be defined
in arch/avr32/config.mk rather than board header files.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Upon further inspection of relevant parts of the architecture, the
maximum SPL binary size is 220KiB.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Create a new file, include/configs/ti_omap3_common.h, for everything
common to the OMAP3 SoC leaving just the board specific part to board
configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have
1 bank, but for some boards should be interesting that we can define
CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of
DRAM banks if is not already defined. This is useful for some OMAP3 boards
where the DRAM initialitzation is only at u-boot level.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
The ELM hardware engine wihich is used for ECC error detections is not present
on OMAP3 SoC, so move the CONFIG_SPL_NAND_AM33XX_BCH from ti_armv7_common.h to
SoC configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Follow the pattern ti_<processor family>_common.h used by other TI processors
to be coherent. So just rename omap5_common.h to ti_omap5_common.h.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Follow the pattern ti_<processor family>_common.h used by other TI processors
to be coherent. So just rename omap4_common.h to ti_omap4_common.h.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.
So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.
Also add their details in README.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
read at 400KHz.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
findftd is currently setting fdtfile to undefined for the beagle c4, select omap3-beagle.dtb instead
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
This patch enables ethernet support in ARMv8 foundation model. The ARMv8
foundation model supports a SMSC91C111 integrated MAC and PHY module
which is present at base address 0x01A000000.
The previous implementation had enabled SMSC9115 ethernet controller
which is not present on the ARMv8 foundation model.
Tested on ARMv8 foundation model v1 and v2 by running ping/tftp
between the foundation model and the host PC via a bridged network.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Provide default Poll Timeout value for Trats2 board.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Disable L2 caches for Trats and Trats2 devices.
It turns out that for data downloading with thordown command L2 cache
disablement brings a significant speed improvement.
rootfs - 400 MiB:
- L2 cache enabled: 2.69 MiB/s
- L2 cache disabled: 5.56 MiB/s
Such improvement is possible due to reduction of the need to invalidate
redundant data, which resides in L2 cache.
Since the sent USB request size at once is 512B (L1 - 32 KiB in total) -
one can be quite confident that it is already available in L1 and L2 can
be disabled.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds extra dfu_alt_info entries to support storing the whole BOOT
, DATA and UMS partitions.
This allows upgrade of uImage and device tree blob (dtb) files at once.
Now it is also possible to store ext4 rootfs prepared with well established
linux tools (like mkfs.ext4).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
SolidRun has designed the Hummingboard board based on mx6q/dl/solo.
Add the initial support for the mx6 solo variant.
More information about this hardware can be found at:
http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
(Carrier-One was the previous name of Hummingboard).
Based on the work from Jon Nettleton <jon.nettleton@gmail.com>.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Access the OneNAND 1KiB window on the VPAC270 as an SRAM instead of accessing
it as a burst-RAM. This fixes a problem where the board failed to reboot
sometimes as the CPU couldn't start executing from the OneNAND 1KiB window.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
controller, connected to HSIC Phy of USB host controller via USB3503 hub.
This patch uses board specific board_usb_init function to perform reset
sequence for USB3503 hub and enables the relevant config options for
network to work.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Include "mx6_common.h" so that some ARM errata are applied and also the
vddsoc regulator can be changed.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Change the default environment to use zImage instead of uImage, this
requires changes to the default environment to load a file named
zImage instead of uImage, and to use the 'bootz' command instead of
'bootm' when booting the kernel.
The zImage works for FSL Linux's kernel fork versions 3.0.35, 3.10.9,
and 3.10.17; this also works fine for mainline kernels.
Signed-off-by: John Weber <rjohnweber@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
A new 'update_emmc_firmware' target is added to allow for easy U-Boot
update in the eMMC as it has secury boot partition and this needs
specific handling on how to program the specific partition.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The Versatiles come up with the primary UART set to ttyAMA0 at
38400 baud, and unless we pass this to the kernel it will assume
it is set to 9600 baud which will be quite awkward for the
terminal, let's try to be helpful and inform the kernel what
setting is used.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
Enabled default dts files on respective pre-board config
files this is way MAKEALL will works. and it's upto user
to build specific dts by specifying at build time.
$ make zynq_zc70x_config
$ make --> with default dts zynq-zc702.dts
or
$ make DEVICE_TREE=zynq-zc702 --> Same configuration with zynq-zc706.dts
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
CONFIG_FIT_SIGNATURE - signature node support in FIT image
CONFIG_RSA - RSA lib support
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides a basic fdt support for zynq u-boot.
zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.
u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed
Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Defined default env. for autoboot FIT image from
respective boot devices.
Default settings:
fit_image=fit.itb
load_addr=0x2000000
fit_size=0x800000
flash_off=0x100000
nor_flash_off=0xE2100000
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not
needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM010:
- 1Gb DDR3
- 1Mb SST SPI flash
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size SD/MMC card cage
- 10/100/1000 Ethernet
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User I/O (50 per connector)
- Configurable as up to 48 LVDS pairs or 100 single-ended I/O
Misc:
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod
- 33.33 MHz oscillator
- User LED and push switch
For more info - http://zedboard.org/product/microzed
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.
Enable EEPROM support for zc70x boards.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.
ZC702-:
APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
- IIC Bus Headers/HUB
- 1 CAN with Wake on CAN
- USB-UART
Video/Display:
- HDMI Video OUT
- 8X LEDs
Control & I/O:
- 3 User Push Buttons
- 2 User Switches
- 8 User LEDs
For more info on zc702 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
ZC706-:
APSOC:
- XC7Z045 FFG900 -2 AP SoC
Memory:
- DDR3 Component Memory 1GB (PS)
- DDR3 SODIM Memory 1GB (PL)
- 2X16MB Quad SPI Flash (dual parallel)
- IIC - 1 KB EEPROM
Connectivity:
- PCIe Gen2x4
- SFP+ and SMA Pairs
- GigE RGMII Ethernet (PS)
- USB OTG 1 (PS) - Host USB
- IIC Bus Headers/HUB (PS)
- 1 CAN with Wake on CAN (PS)
- USB-UART
Video/Display:
- HDMI 8 color RGB 4.4.4 1080P-60 OUT
- HDMI IN 8 color RGB 4.4.4
Control & I/O:
- 2 User Push Buttons/Dip Switch, 2 User LEDs
- IIC access to GPIO
- SDIO (SD Card slot)
- 3 User Push Buttons, 2 User Switches, 8 User LEDs
For more info on zc706 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
zynq.h -> zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.
zynq.h is no longer exists hense removed from boards.cfg
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Bounce buffer implementation takes care of proper data buffer alignemt
and correct flush/invalidation of data cache at once so we no longer
depend on input data variety and make sure CPU and MMC controller deal
with expected data in case of enabled data cache.
Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in
board configuration, otherwise corresponding library won't be compiled
and linker will fail to build resulting executable.
Difference since v1 - fixed compile-time warning with type casting to
"void *":
Slight edit to remove UTF8 characters in the commit message.
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
====
passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier
from pointer target type
====
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Amar <amarendra.xt@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Andy Fleming <afleming@gmail.com>
SH4 and SH4A are compatible. But some instructions are different from these.
In Linux kernel, It is treated as a separate CPU, but for now, I think that
there is no need to divide especially in the U-Boot.
This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4.
And this fix white space.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add a simple TPM emulator for sandbox. It only supports a small subset of
TPM operations. However, these are enough to perform common tasks.
Note this is an initial commit to get this working, but it could use
cleaning up (for example constants instead of open-coded values).
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Provide a way to use any host file or device as a block device in U-Boot.
This can be used to provide filesystem access within U-Boot to an ext2
image file on the host, for example.
The support is plumbed into the filesystem and partition interfaces.
We don't want to print a message in the driver every time we find a missing
device. Pass the information back to the caller where a message can be printed
if desired.
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
- Removed change to part.c get_device_and_partition()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
All prerequisites are already available, so why not enable 8-bit
access - it is a matter of a define in the board file only.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
CONFIG_SYS_HZ of SH2 is not used as frequency of base timer. This is the
correct clock of CMT.
This changes from CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ, in order to use
CONFIG_SYS_HZ as clock of CMT.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CONFIG_SH4 was already defined in arch/sh/sh4/config.mk.
This removes CONFIG_SH4 from board config files of SH4.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CONFIG_SH3 was already defined in arch/sh/sh3/config.mk.
This removes CONFIG_SH3 from board config files of SH3.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CONFIG_SH2 was already defined in arch/sh/sh2/config.mk.
This removes CONFIG_SH2 from board config files of SH2.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CONFIG_SH is defined in arch/sh/config.mk.
It is not necessary to define it in each board
header config header file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Following commit "arm: omap3: Enable clocks for peripherals only if they are
used" (f33b9bd398) it is now necessary to enable
clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for
scf0403 lcd support.
Enable GPIO bank 5 clocks.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Commit f33b9bd398 breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.
Signed-off-by: Tom Rini <trini@ti.com>
With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Due to the i2c mux rework in u-boot we now have only to specify the
busnumber and not the whole mux configuration.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
The board is similar to the standard km_kirkwood board. From a
u-boot point of view, the only difference is an increased
256 MiB DRAM (128M16). A board based on this design is for
example the SUP12.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.
This changes following boards:
- mx6sabreauto
- mx6sabresd
- wandboard
- udoo
- nitrogen6x
- cgtqmx6eval
The reasoning, as explained by Hui Liu, is:
,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
This adds following new targets:
- update_nand_kernel
- update_nand_fdt
- update_nand_filesystem
and to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
This fixes a build break due to excessively large NAND data structures.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.
So, Increase TCH as 0x8 i.e. 8 ip_clk.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.
So, use CONFIG_SPL_NAND_BOOT config.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.
Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.
The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With changes to the rtl8169 ethernet to improve cache support, we have
needed additional cache functions for mpc8245. As the board maintainer
has been unresponsive, remove this board.
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Add config to support bank address register.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix the timeout issue after running "bootp" command in u-boot
console. For example you see "EHCI timed out on TD- token=0x...".
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).
Signed-off-by: Jim Lin <jilin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
DT kernel requires CONFIG_OF_LIBFDT. 'bootm' needs to know DT location.
In addition, fix kernel console device and enable U-Boot long help.
Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
Initial configuration has worng address of the second chip.
There is an alias for the 1st chip at 0x02000000 in earlier
verions of LP-8x4x, so the boot normally.
However, new LP-8x4xs have a bigger 1st flash chip, and hang on
boot without this patch.
Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
