mirror of
https://github.com/brain-hackers/u-boot-brain
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powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Using the TPL/SPL method to booting from 8k page NAND flash. - Add 256kB size SRAM tlb for second step booting; - Add spl.c for TPL image boot; - Add spl_minimal.c for minimal SPL image; - Add C29XPCIE_NAND configure; - Modify C29XPCIE.h for nand config and enviroment; Signed-off-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Po Liu
York Sun
parent
6609916efb
commit
eb6b458cef
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@ -3,8 +3,23 @@
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#
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# SPDX-License-Identifier: GPL-2.0+
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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obj-y += spl_minimal.o tlb.o law.o
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else
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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obj-y += c29xpcie.o
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obj-y += cpld.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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endif
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@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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@ -129,3 +130,4 @@ U_BOOT_CMD(
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"cpld_cmd dump - display the CPLD registers\n"
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#endif
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);
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#endif
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77
board/freescale/c29xpcie/spl.c
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77
board/freescale/c29xpcie/spl.c
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@ -0,0 +1,77 @@
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <nand.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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ulong get_effective_memsize(void)
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{
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return CONFIG_SYS_L2_SIZE;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *)CONFIG_SPL_GD_ADDR;
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bd_t *bd;
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memset(gd, 0, sizeof(gd_t));
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bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
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bd->bi_memsize = CONFIG_SYS_L2_SIZE;
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probecpu();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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/* relocate environment function pointers etc. */
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = 1;
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i2c_init_all();
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_NAND_BOOT
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puts("TPL\n");
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#else
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puts("SPL\n");
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#endif
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nand_boot();
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}
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63
board/freescale/c29xpcie/spl_minimal.c
Normal file
63
board/freescale/c29xpcie/spl_minimal.c
Normal file
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@ -0,0 +1,63 @@
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc85xx.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
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set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
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set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
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#endif
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot...\n");
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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puts("SPL\n");
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_SPL_BUILD
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 1, BOOKE_PAGESZ_64M, 1),
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@ -42,6 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256K, 1),
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#endif
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#endif
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SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
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@ -49,7 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 4, BOOKE_PAGESZ_64K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_64K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
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@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 7, BOOKE_PAGESZ_256K, 1),
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#ifdef CONFIG_SYS_RAMBOOT
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#if defined(CONFIG_SYS_RAMBOOT) || \
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(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
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CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 9, BOOKE_PAGESZ_256M, 1),
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#endif
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 12, BOOKE_PAGESZ_256K, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -798,6 +798,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
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Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
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Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
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Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
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Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
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Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
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Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
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Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
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@ -23,6 +23,49 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#ifdef CONFIG_NAND
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#define CONFIG_SPL
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#define CONFIG_TPL
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
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#endif
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_TPL_PAD_TO 0x20000
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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@ -31,8 +74,14 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* High Level Configuration Options */
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@ -130,6 +179,10 @@
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(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
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#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_NO_FLASH
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#endif
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/*
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* IFC Definitions
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*/
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@ -183,7 +236,7 @@
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
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/* 8Bit NAND Flash - K9F1G08U0B */
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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@ -215,6 +268,23 @@
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#define CONFIG_SYS_NAND_DDR_LAW 11
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/* Set up IFC registers for boot location NOR/NAND */
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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@ -230,6 +300,7 @@
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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/* CPLD on IFC, selected by CS2 */
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000
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@ -269,7 +340,44 @@
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
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#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
|
||||
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
|
@ -278,6 +386,10 @@
|
|||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
|
|
@ -364,6 +476,16 @@
|
|||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
|
||||
#else
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
|
||||
#endif
|
||||
#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user