Commit Graph

3449 Commits

Author SHA1 Message Date
Stefan Roese
c7f69c3402 ppc4xx: Make output a little shorter on I2C bootrom detection
Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".

This patch also has a little code cleanup integrated.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-09 12:18:54 +01:00
Stefan Roese
654f38b3a3 ppc4xx: Make output a little shorter on PCIe detection
Now not max 3 lines but 2 lines are printed per PCIe port.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-05 07:43:05 +01:00
Stefan Roese
3d6cb3b24a ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support
This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-03 12:08:28 +01:00
Stefan Roese
5d96d40d3f ppc4xx: Fix acadia_nand build problem
Since the cache handling functions were moved from start.S into cache.S
the acadia NAND booting Makfile needs to be adapted accordingly.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
ea2e142843 ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
3db93b8bed ppc4xx: Enable CPU POST test for 4xx with dcache enabled
Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of self modifying code. This is done via the new change_tlb() function.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
f71b2888b4 ppc4xx: Change 4xx POST ethernet test to handle cached memory too
This patch enables the 4xx EMAC POST driver to work too, when dcache is
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
a268590406 ppc4xx: Remove temporary TLB entry in POST cache test only for 440
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
ff768cb168 ppc4xx: Change 4xx ethernet driver to handle cached memory too
This patch enables the 4xx EMAC driver to work too, when dcache is
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
483e09a223 ppc4xx: Add change_tlb function to modify I attribute of TLB(s)
This function is used to either turn cache on or off in a specific
memory area.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
d25dfe08fb ppc4xx: Remove cache definition from 4xx board config files
All 4xx board config files don't need the cache definitions anymore.
These are now defined in common headers.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
9b94ac61d2 ppc4xx: Rework 4xx cache support
New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
06713773da ppc4xx: Remove compiler warning from previous commit
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
6fa397df67 ppc4xx: Remove temporary TLB entry in POST cache test
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
1338e6a818 ppc4xx: Change autonegotiation timeout from 4 to 5 seconds
I lately noticed, that newer 4xx board with GBit support sometimes don't
finish link autonegotiation in 4 seconds. Changing this timeout to 5
seconds seems fine here.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
2d83476a4c ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends
This patch changes all in32/out32 calls to use the recommended in_be32/
out_be32 macros instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
7d47cee2cc ppc4xx: Fix POST ethernet test for Haleakala
The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
f10493c6d7 ppc4xx: Correct UART input clock calculation and passing to fdt
We now use a value in the gd (global data) structure for the UART input
frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
in get_sys_info().

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
353f2688b4 ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Eugene O'Brien
9f798766aa ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
afe9fa59cb ppc4xx: Add SNTP support to AMCC Katmai, Kilauea & Makalu boards
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
3248f63ad8 ppc4xx: Rework of 4xx serial driver (4)
Change 4xx_uart.c:

- Use in_8/out_8 macros instead of in8/out8
- No need for UART_BASE marco anymore, now really handled via function
  parameter
- serial_init_common() introduced
- Further coding style cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
e61cb8163a ppc4xx: Rework of 4xx serial driver (3)
Change all linker scripts to reference the changed driver name iop480_uart.o.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
882ae41274 ppc4xx: Rework of 4xx serial driver (2)
Change all linker scripts to reference the changed driver name 4xx_uart.o.

Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
ad31e40bed ppc4xx: Rework of 4xx serial driver (1)
This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
764e7417ee ppc4xx: Correct UART input clock calculation and passing to fdt
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
211ea91ac6 ppc4xx: Add initial AMCC Makalu 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
fa8aea2045 ppc4xx: Add freqUART to CPU speed detection
This value is needed later for the device tree configuration of
the uart clock.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
837c730b4d ppc: Small Kilauea cleanup of config file
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
758c037aee rtc: Add Xicor/Intersil X1205 RTC support
This patch adds support for the Xicor/Intersil X1205 RTC used on the
AMCC Makalu eval board. This driver is basically cloned from the Linux
driver version (2.6.23).

This patch also introduces the Linux bcd.h header for the BCD2BIN/
BIN2BCD conversions. In the future some of the other U-Boot RTC driver
should be converted to also use this header instead of implementing
their own local copy of these functions/macros.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
770c7af580 ppc4xx: Fix size setup in Kilauea DDR2 init routine
The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.

This patch also does a little cleanup and adds a comment here.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Eugene O'Brien
f6ba9b5660 ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors
CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
c36c681603 ppc4xx: Change inbound PCIe location for endpoint tests on Katmai
On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
is the internal SRAM. Since I now ported and tested this endpoint mode
on Kilauea successfully to map to 0 (SDRAM), I also changed this for
Katmai.

Yucca will stay at internal SRAM for now. Not sure if somebody relies on
this setup.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
5cb4af4791 ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.

In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
d4cb2d1794 ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
fd671802b6 ppc4xx: Enable device tree support (fdt) on Kilauea per default
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.

This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
4994ffd890 ppc4xx: Add additional debug info to 4xx fdt support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
db3232ddb0 ppc4xx: Fix small merge problems with CPCI440 and Acadia boards
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
1941cce71b ppc4xx: Fix small merge problem in 4xx_enet.c
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
566806ca1a ppc4xx: Add initial AMCC Kilauea 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
dbbd125721 ppc4xx: Add PPC405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
1d7b874e9c ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4f14ed6230 ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
a424a8bb29 POST: Add 405EX support to 4xx UART POST test
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4f2e92c11f DTT: Prepare DS1775 driver for use of different I2C addresses
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
19e93b1e16 ppc4xx: 4xx_pcie: Change PCIe status output to match common style
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
ff68f66bcb ppc4xx: 4xx_pcie: Disable debug output as default
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
97923770cb ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4dbee8a90d ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.

One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.

This patch adds debug output to the 4xx pcie driver too.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00