- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
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Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips
- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c
The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.
I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.
Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add network driver for Microsemi Ethernet switch.
It is present on ServalT SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add network driver for Microsemi Ethernet switch.
It is present on Jaguar2 SoCs.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2-v3:
- add more commit message for s17
Changes for v4-v5:
- coding style cleanup
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.
To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.
Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).
For example:
STM32MP> fuse read 1 0xf8 8
Reading bank 1:
Word 0x000000f8: 000000ee 00000092 000000c0 00000002
Word 0x000000fc: 000000f2 00000080 00000002 00000033
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with STPMIC1 datasheet
s/MAIN_CONTROL_REG/MAIN_CR/g
s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
s/MASK_RESET_LDOS/LDOS_MRST_CR/g
s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
s/USB_CTRL_REG/BST_SW_CR/g
s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Prepare file modification for kernel alignment and
rename driver to stpmic1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
(see STPMIC1 datasheet / chapter 5.3 Buck converters)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32
The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power
The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This adds support for the Gigadevice gd25lq128 ID needed on the
upcoming libretech-ac board.
SPI_NOR_QUAD_READ is not set since it has not been tested in Quad
mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.
Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.
[1] http://www.ti.com/lit/pdf/sprui30
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL
is enabled. Use static platdata instead to save space.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The ofdata_to_platdata function should not be called if OF_CONTROL is
not enabled because fdtdec_* calls will fail. Block the function with
OF_CONTROL
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
cpsw_phy_sel() is a configuration step that should not be in
ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data
structure so that it is accessible in _probe. Then move the call of
cpsw_phy_sel() to _probe.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
DMSC can use certain amount of msmc memory available in the
system. Also certain part of msmc memory can be marked as L3
cache using board config. But users might not know what size
is being used and the remaining available msmc memory. In order
to fix this TISCI protocol provides a messages that can query
the available msmc memory in the system. Add support for this
message.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enhance the netcp driver to support phys that can be configured
for internal delay (rgmii-id, rgmii-rxid, rgmii-txid)
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch update the behavior introduced by
commit 96907c0fe5 ("dm: spi: Read default speed and mode values from DT")
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_* but instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Remove also use in boards of the value speed=0 (no more supported)
for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0.
DT values will be always used when available (full DM support of
SPI slave with available DT node) even if speed and mode are requested;
for example in splash screen support (in splash_sf_read_raw)
or in SPL boot (in spl_spi_load_image).
The caller of spi_get_bus_and_cs() no more need to force speed=0.
But the current behavior don't change if the SPI slave is not
present (device with generic driver is created automatically)
or if platdata is used (CONFIG_OF_PLATDATA).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Replace the ad-hoc erase operation implementation with a simple spi_mem_op
implementation of the same functionality. This is a minor optimization and
removal of the ad-hoc code.
This however also changes the behavior of the execution of the erase
opcode from two separate transfer requests to the SPI NOR driver to
one transfer request to the SPI NOR driver. The former was how U-Boot
behaved before the SPI NOR framework was imported and the later was
introduced by the SPI NOR framework. The former is more optimal, so
keep that.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
Tested-by: Ashish Kumar <Ashish.kumar@nxp.com>
Update to prevent a byte of zeros being transmitted between
each byte in the tx buffer when providing both a tx buffer
and a rx buffer.
Signed-off-by: Jared Bents <jared.bents@rockwellcollins.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
A Coverity robot reported an integer handling issue
(OVERFLOW_BEFORE_WIDEN) in the potentially overflowing expression:
(mtd_div_by_ws(mtd->size, mtd) - mtd_div_by_ws(offs, mtd)) *
mtd_oobavail(mtd, ops)
While such overflow will certainly never happen due to the numbers
handled, it is cleaner to fix this operation anyway.
The problem is that all the maths include 32-bit quantities, while the
result is stored in an explicit 64-bit value.
As maxooblen will just be compared with a size_t, let's change the
type of the variable to a size_t. This will not fix anything but will
clarify a bit the situation. Then, do an explicit cast to fix Coverity
warning.
Addresses-Coverity-ID: 184180 ("Integer handling issues")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Add Macronix MX66U2G45F flash device description.
This is a 256 MiB part.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Vignesh R <vigneshr@ti.com>
[jagan: use 'g' instead of 'f' in flash name]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Now the "spi-flash" compatible has been removed in the DTS files,
remove this compatible from sf_probe to finally use the Linux "jedec,spi-nor"
compatible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for SPANSION s25fl064l
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Vignesh R <vigneshr@ti.com>
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support
with the latest Linux version (v5.0-rc3) plus the chip supported posted
on the MTD list. Only the currently in U-Boot available chip is
supported with this sync.
The changes for the GD5F1GQ4UExxG are:
- Name of NAND device changed to better reflect the real part
- OOB layout changed to only reserve 1 byte for BBT
- Use ECC caps 8bits/512bytes instead of 8bits/2048bytes
- Enhanced ecc_get_status() function to determine and report
a more fine grained bit error status
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Use quad write if SPI_TX_QUAD flag is set.
Tested quad write on Stratix 10 SoC board (Micron
serial NOR flash, mt25qu02g)
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The kirkwood devices are compatible with this driver.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix the worng include and offset macros.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This fixes a compile error on kirkwood.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
With board_ahci_enable() implementation for Armada 38x in place we can
now enable 38x support in the ahci_mvebu driver.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds DM support to the Armada XP SATA driver. This is needed
to enable CONFIG_BLK on this platform. It adds the SATA controller as
AHCI device, which is strictly speaking not correct, as the controller
is not AHCI compatible. But the U-Boot AHCI uclass interface enables
the usage of this DM driver and the creation of the corresponding BLK
devices.
This conversion is done to get rid of the compile warning:
Reviewed-by: Chris Packham <judge.packham@gmail.com>
===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
The generic wdt_start API expects to be called with the timeout in
milliseconds. Update the orion_wdt driver to accept a timeout in
milliseconds and use the clock rate specified in the dts to convert the
timeout to an appropriate value for the timer reload register.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
When run from the SPL the mvebu targets are using the hardware default
offset for the SoC peripherals. devfdt_get_addr_size_index() understands
how to deal with this via dm_get_translation_offset() so use this
instead of fdtdec_get_addr_size_auto_noparent().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The function dm_ofnode_pre_reloc should be used instead
of the function dm_fdt_pre_reloc and avoid duplicated code.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
v2019.04-rc3 sandbox U-Boot fails to boot when compiled with
-fsanitize=address and linked against -lasan, reporting [1].
Git bisecting shows that the issue is contributed by v2019.01 commit
1678754f5e ("core: ofnode: Fix ofnode_get_addr_index function").
The root cause seems to be the mismatch between sizeof(u64) and
sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the
size argument of both of_get_address() and fdtdec_get_addr_size_fixed()
is optional, we can pass NULL in its place, avoiding the problem.
[1] Backtrace reported by ASAN (gcc 8.1.0):
$> ./u-boot -d arch/sandbox/dts/sandbox.dtb
[..]
Reviewed-by: Simon Glass <sjg@chromium.org>
=================================================================
==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffcc2331140 at pc 0x0000004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70
WRITE of size 8 at 0x7ffcc2331140 thread T0
#0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154
#1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263
#2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422
#3 0x4dccd8 in device_probe drivers/core/device.c:407
#4 0x753170 in eth_initialize net/eth-uclass.c:428
#5 0x47d9bf in initr_net common/board_r.c:557
#6 0x6bcfa7 in initcall_run_list lib/initcall.c:30
#7 0x47e1fe in board_init_r common/board_r.c:859
#8 0x4060e5 in main arch/sandbox/cpu/start.c:356
#9 0x7fb8d135482f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f)
#10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8)
Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame
#0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255
This frame has 3 object(s):
[32, 36) 'size' <== Memory access at offset 32 partially overflows this variable
[96, 100) 'flags'
[160, 168) 'node'
HINT: this may be a false positive if your program uses some custom stack unwind mechanism or swapcontext
(longjmp and C++ exceptions *are* supported)
SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154 in of_get_address
Shadow bytes around the buggy address:
0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1
0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2
0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00
=>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2
0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3
0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3
0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00
Shadow byte legend (one shadow byte represents 8 application bytes):
Addressable: 00
Partially addressable: 01 02 03 04 05 06 07
Heap left redzone: fa
Freed heap region: fd
Stack left redzone: f1
Stack mid redzone: f2
Stack right redzone: f3
Stack after return: f5
Stack use after scope: f8
Global redzone: f9
Global init order: f6
Poisoned by user: f7
Container overflow: fc
Array cookie: ac
Intra object redzone: bb
ASan internal: fe
Left alloca redzone: ca
Right alloca redzone: cb
==10998==ABORTING
'To' list:
git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \
sed 's/.*-by: //' | sort | uniq -c | sort -rn
10 Simon Glass <sjg@chromium.org>
3 Mario Six <mario.six@gdsys.cc>
2 Martin Fuzzey <mfuzzey@parkeon.com>
2 Marek Vasut <marek.vasut+renesas@gmail.com>
1 Tom Rini <trini@konsulko.com>
1 Masahiro Yamada <yamada.masahiro@socionext.com>
1 Keerthy <j-keerthy@ti.com>
1 Jens Wiklander <jens.wiklander@linaro.org>
1 Bin Meng <bmeng.cn@gmail.com>
Fixes: 1678754f5e ("core: ofnode: Fix ofnode_get_addr_index function")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Change the function syscon_regmap_lookup_by_phandle()
introduced by commit 6c3af1f24e ("syscon: dm: Add a
new method to get a regmap from DTS") to have
Linux-compatible syscon API.
Same modification than commit e151a1c288 ("syscon: add
Linux-compatible syscon API") solves issue when the node
identified by the phandle has several compatibles and is
already bound to a dedicated driver.
See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon
interface from platform devices").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some binding define child node gpio-controller without compatible property.
This patch avoid to bind the pinconfig uclass to these node.
For example, the binding for st,stm32-pinctrl
(./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO
controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl)
but without compatible (as it is not mandatory).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In case of system with several pin-controller device, probe the first
UCLASS_PINCTRL by seq number (defined by alias) to avoid race condition
with I2C PINCONTROL driver for GPIO expander (GPIO expander need I2C bus,
I2C driver need PINCONFIG).
Signed-off-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit 5ff7768892.
As noted in the comment, the function pinctrl_decode_pin_config_dm()
only served as a temporary solution.
Since the function has no users anymore, we can remove it again.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We can remove the pre reloc property in SPL and TPL device-tree:
- u-boot,dm-pre-reloc
- u-boot,dm-spl
- u-boot,dm-tpl
As only the needed node are kept by fdtgrep (1st pass).
The associated function (XXX_pre_reloc) are simple for SPL/TPL:
return always true.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.
The initial driver supports:
- MEM_TO_MEM (TR mode)
- DEV_TO_MEM (Packet mode)
- MEM_TO_DEV (Packet mode)
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.
Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager Mode
TI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.
The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while TI-SCI Message
Protocol supports only one combined operation (allocate+configure).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI firmware.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
The chip_desc.enable field is used only for muxes, not for switches.
Document it and remove the unused values.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher<hs@denx.de>
The Kconfig help has not been updated while adding PCA9547 and PCA9646.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher<hs@denx.de>
The 'u-boot,i2c-transaction-bytes' device tree property provides
information regarding number of bytes transferred by a device in a
single transaction.
This change is necessary to avoid hanging devices after soft reset.
One notable example is communication with MC34708 device:
1. Reset when communicating with MC34708 via I2C.
2. The u-boot (after reboot -f) tries to setup the I2C and then calls
force_idle_bus. In the same time MC34708 still has some data to be sent
(as it transfers data in 24 bits chunks).
3. The force_idle_bus() is not able to make the bus idle as 8 SCL
clocks may be not enough to have the full transmission.
4. We end up with I2C inconsistency with MC34708.
This PMIC device requires 24+ SCL cycles to make finish any pending I2C
transmission.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reset and initialize the PHY once in the probe() function rather than
doing it over and over again is start() function. This requires us to
keep the clock enabled while the driver is in use. This significantly
reduces the time between transfers as the PHY doesn't have to restart
autonegotiation between transfers, which takes forever.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Synchronize R-Car Gen3 pin control tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Synchronize R-Car Gen2 pin control tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783,
has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement
similar fix for U-Boot. The difference here is that the SoC
ES matching has to be implemented manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add pin control tables for R8A77965 from Linux 5.0 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
There exists code in drivers/common/common.c to read the dr_mode
from the device tree. This patch converts this driver to use that
function to initialize the driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
Drop the counter, it has no meaning other than being the order in which
the interface is found; the name assigned to the USB host controller
interface is a better indicator.
Example of the original output:
> USB0: USB EHCI 1.10
> scanning bus 0 for devices... 2 USB Device(s) found
> scanning usb for storage devices... 1 Storage Device(s) found
Patched output:
> Bus usb@ee080100: USB EHCI 1.10
> scanning bus usb@ee080100 for devices... 2 USB Device(s) found
> scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
I've noticed that the first ethernet packet after PHY link establishment
is not tranferred correctly most of the time on my AT91SAM9G25 board.
Here I usually see a timeout of a few seconds, which is quite
annoying.
Adding a small delay (10ms in this case) after the link establishment
helps to solve this problem. With this patch applied, this timeout
on the first packet is not seen any more.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
more. The WD timeout value can be provided via the "timeout-sec" DT
property. If not provided this way, the default value of 2 seconds will
be used.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
This patch fixes the timer register setup in at91_wdt_start() to
correctly configure the register again. The input timeout value is
now in milli-seconds instead of seconds with the new watchdog API.
Make sure to take this into account and only use a max timeout
value of 16 seconds as appropriate for this SoC.
Also the check against a lower timeout value than 0 is removed. This
check makes no sense, as the timeout value is unsigned.
Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Before printk.h was introduced and MTDDEBUG was removed,
pr_crit() was calling MTDDEBUG(), which was since then
replaced by the current pr_debug().
pr_debug is more appropriate here.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a new definition for ubi_assert and keep
the original one in an ifndef __UBOOT__.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
a delay of phy-reset-post-delay milliseconds will be observed after the
phy-reset-gpios has been toggled. Can be omitted thus no delay is
observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
