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firmware: ti_sci: Add support for NAVSS resource management

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Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.

This patch adds support for requesting and configuring such resources
from TI-SCI firmware.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
This commit is contained in:
Grygorii Strashko 2019-02-05 17:31:21 +05:30 committed by Tom Rini
parent 02f173ca15
commit fd6b40b1ba
4 changed files with 1692 additions and 12 deletions
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2
arch/arm/dts/k3-am65-wakeup.dtsi
View File

@ -7,7 +7,7 @@
&cbass_wakeup {
dmsc: dmsc {
compatible = "ti,k2g-sci";
compatible = "ti,am654-sci";
ti,host-id = <12>;
#address-cells = <1>;
#size-cells = <1>;

760
drivers/firmware/ti_sci.c
View File

@ -12,6 +12,7 @@
#include <errno.h>
#include <mailbox.h>
#include <dm/device.h>
#include <linux/compat.h>
#include <linux/err.h>
#include <linux/soc/ti/k3-sec-proxy.h>
#include <linux/soc/ti/ti_sci_protocol.h>
@ -31,16 +32,37 @@ struct ti_sci_xfer {
u8 rx_len;
};
/**
* struct ti_sci_rm_type_map - Structure representing TISCI Resource
* management representation of dev_ids.
* @dev_id: TISCI device ID
* @type: Corresponding id as identified by TISCI RM.
*
* Note: This is used only as a work around for using RM range apis
* for AM654 SoC. For future SoCs dev_id will be used as type
* for RM range APIs. In order to maintain ABI backward compatibility
* type is not being changed for AM654 SoC.
*/
struct ti_sci_rm_type_map {
u32 dev_id;
u16 type;
};
/**
* struct ti_sci_desc - Description of SoC integration
* @host_id: Host identifier representing the compute entity
* @max_rx_timeout_us: Timeout for communication with SoC (in Microseconds)
* @max_msg_size: Maximum size of data per message that can be handled.
* @default_host_id: Host identifier representing the compute entity
* @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds)
* @max_msgs: Maximum number of messages that can be pending
* simultaneously in the system
* @max_msg_size: Maximum size of data per message that can be handled.
* @rm_type_map: RM resource type mapping structure.
*/
struct ti_sci_desc {
u8 host_id;
int max_rx_timeout_us;
u8 default_host_id;
int max_rx_timeout_ms;
int max_msgs;
int max_msg_size;
struct ti_sci_rm_type_map *rm_type_map;
};
/**
@ -136,7 +158,7 @@ static inline int ti_sci_get_response(struct ti_sci_info *info,
int ret;
/* Receive the response */
ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_us);
ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms);
if (ret) {
dev_err(info->dev, "%s: Message receive failed. ret = %d\n",
__func__, ret);
@ -1441,6 +1463,147 @@ static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle)
return ret;
}
static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
u16 *type)
{
struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
bool found = false;
int i;
/* If map is not provided then assume dev_id is used as type */
if (!rm_type_map) {
*type = dev_id;
return 0;
}
for (i = 0; rm_type_map[i].dev_id; i++) {
if (rm_type_map[i].dev_id == dev_id) {
*type = rm_type_map[i].type;
found = true;
break;
}
}
if (!found)
return -EINVAL;
return 0;
}
/**
* ti_sci_get_resource_range - Helper to get a range of resources assigned
* to a host. Resource is uniquely identified by
* type and subtype.
* @handle: Pointer to TISCI handle.
* @dev_id: TISCI device ID.
* @subtype: Resource assignment subtype that is being requested
* from the given device.
* @s_host: Host processor ID to which the resources are allocated
* @range_start: Start index of the resource range
* @range_num: Number of resources in the range
*
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
u16 *range_start, u16 *range_num)
{
struct ti_sci_msg_resp_get_resource_range *resp;
struct ti_sci_msg_req_get_resource_range req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
u16 type;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_RESOURCE_RANGE,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(dev, "Message alloc failed(%d)\n", ret);
return ret;
}
ret = ti_sci_get_resource_type(info, dev_id, &type);
if (ret) {
dev_err(dev, "rm type lookup failed for %u\n", dev_id);
goto fail;
}
req.secondary_host = s_host;
req.type = type & MSG_RM_RESOURCE_TYPE_MASK;
req.subtype = subtype & MSG_RM_RESOURCE_SUBTYPE_MASK;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(dev, "Mbox send fail %d\n", ret);
goto fail;
}
resp = (struct ti_sci_msg_resp_get_resource_range *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp)) {
ret = -ENODEV;
} else if (!resp->range_start && !resp->range_num) {
ret = -ENODEV;
} else {
*range_start = resp->range_start;
*range_num = resp->range_num;
};
fail:
return ret;
}
/**
* ti_sci_cmd_get_resource_range - Get a range of resources assigned to host
* that is same as ti sci interface host.
* @handle: Pointer to TISCI handle.
* @dev_id: TISCI device ID.
* @subtype: Resource assignment subtype that is being requested
* from the given device.
* @range_start: Start index of the resource range
* @range_num: Number of resources in the range
*
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle,
u32 dev_id, u8 subtype,
u16 *range_start, u16 *range_num)
{
return ti_sci_get_resource_range(handle, dev_id, subtype,
TI_SCI_IRQ_SECONDARY_HOST_INVALID,
range_start, range_num);
}
/**
* ti_sci_cmd_get_resource_range_from_shost - Get a range of resources
* assigned to a specified host.
* @handle: Pointer to TISCI handle.
* @dev_id: TISCI device ID.
* @subtype: Resource assignment subtype that is being requested
* from the given device.
* @s_host: Host processor ID to which the resources are allocated
* @range_start: Start index of the resource range
* @range_num: Number of resources in the range
*
* Return: 0 if all went fine, else return appropriate error.
*/
static
int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
u16 *range_start, u16 *range_num)
{
return ti_sci_get_resource_range(handle, dev_id, subtype, s_host,
range_start, range_num);
}
/**
* ti_sci_cmd_proc_request() - Command to request a physical processor control
* @handle: Pointer to TI SCI handle
@ -1803,6 +1966,416 @@ static int ti_sci_cmd_get_proc_boot_status(const struct ti_sci_handle *handle,
return ret;
}
/**
* ti_sci_cmd_ring_config() - configure RA ring
* @handle: pointer to TI SCI handle
* @valid_params: Bitfield defining validity of ring configuration parameters.
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
* @index: Ring index.
* @addr_lo: The ring base address lo 32 bits
* @addr_hi: The ring base address hi 32 bits
* @count: Number of ring elements.
* @mode: The mode of the ring
* @size: The ring element size.
* @order_id: Specifies the ring's bus order ID.
*
* Return: 0 if all went well, else returns appropriate error value.
*
* See @ti_sci_msg_rm_ring_cfg_req for more info.
*/
static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
u32 valid_params, u16 nav_id, u16 index,
u32 addr_lo, u32 addr_hi, u32 count,
u8 mode, u8 size, u8 order_id)
{
struct ti_sci_msg_rm_ring_cfg_resp *resp;
struct ti_sci_msg_rm_ring_cfg_req req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_RM_RING_CFG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "RM_RA:Message config failed(%d)\n", ret);
return ret;
}
req.valid_params = valid_params;
req.nav_id = nav_id;
req.index = index;
req.addr_lo = addr_lo;
req.addr_hi = addr_hi;
req.count = count;
req.mode = mode;
req.size = size;
req.order_id = order_id;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "RM_RA:Mbox config send fail %d\n", ret);
goto fail;
}
resp = (struct ti_sci_msg_rm_ring_cfg_resp *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;
fail:
dev_dbg(info->dev, "RM_RA:config ring %u ret:%d\n", index, ret);
return ret;
}
/**
* ti_sci_cmd_ring_get_config() - get RA ring configuration
* @handle: pointer to TI SCI handle
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
* @index: Ring index.
* @addr_lo: returns ring's base address lo 32 bits
* @addr_hi: returns ring's base address hi 32 bits
* @count: returns number of ring elements.
* @mode: returns mode of the ring
* @size: returns ring element size.
* @order_id: returns ring's bus order ID.
*
* Return: 0 if all went well, else returns appropriate error value.
*
* See @ti_sci_msg_rm_ring_get_cfg_req for more info.
*/
static int ti_sci_cmd_ring_get_config(const struct ti_sci_handle *handle,
u32 nav_id, u32 index, u8 *mode,
u32 *addr_lo, u32 *addr_hi,
u32 *count, u8 *size, u8 *order_id)
{
struct ti_sci_msg_rm_ring_get_cfg_resp *resp;
struct ti_sci_msg_rm_ring_get_cfg_req req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_RM_RING_GET_CFG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev,
"RM_RA:Message get config failed(%d)\n", ret);
return ret;
}
req.nav_id = nav_id;
req.index = index;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "RM_RA:Mbox get config send fail %d\n", ret);
goto fail;
}
resp = (struct ti_sci_msg_rm_ring_get_cfg_resp *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp)) {
ret = -ENODEV;
} else {
if (mode)
*mode = resp->mode;
if (addr_lo)
*addr_lo = resp->addr_lo;
if (addr_hi)
*addr_hi = resp->addr_hi;
if (count)
*count = resp->count;
if (size)
*size = resp->size;
if (order_id)
*order_id = resp->order_id;
};
fail:
dev_dbg(info->dev, "RM_RA:get config ring %u ret:%d\n", index, ret);
return ret;
}
static int ti_sci_cmd_rm_psil_pair(const struct ti_sci_handle *handle,
u32 nav_id, u32 src_thread, u32 dst_thread)
{
struct ti_sci_msg_hdr *resp;
struct ti_sci_msg_psil_pair req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_RM_PSIL_PAIR,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "RM_PSIL:Message alloc failed(%d)\n", ret);
return ret;
}
req.nav_id = nav_id;
req.src_thread = src_thread;
req.dst_thread = dst_thread;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "RM_PSIL:Mbox send fail %d\n", ret);
goto fail;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;
fail:
dev_dbg(info->dev, "RM_PSIL: nav: %u link pair %u->%u ret:%u\n",
nav_id, src_thread, dst_thread, ret);
return ret;
}
static int ti_sci_cmd_rm_psil_unpair(const struct ti_sci_handle *handle,
u32 nav_id, u32 src_thread, u32 dst_thread)
{
struct ti_sci_msg_hdr *resp;
struct ti_sci_msg_psil_unpair req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_RM_PSIL_UNPAIR,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "RM_PSIL:Message alloc failed(%d)\n", ret);
return ret;
}
req.nav_id = nav_id;
req.src_thread = src_thread;
req.dst_thread = dst_thread;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "RM_PSIL:Mbox send fail %d\n", ret);
goto fail;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;
fail:
dev_dbg(info->dev, "RM_PSIL: link unpair %u->%u ret:%u\n",
src_thread, dst_thread, ret);
return ret;
}
static int ti_sci_cmd_rm_udmap_tx_ch_cfg(
const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params)
{
struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp *resp;
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_RM_UDMAP_TX_CH_CFG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message TX_CH_CFG alloc failed(%d)\n", ret);
return ret;
}
req.valid_params = params->valid_params;
req.nav_id = params->nav_id;
req.index = params->index;
req.tx_pause_on_err = params->tx_pause_on_err;
req.tx_filt_einfo = params->tx_filt_einfo;
req.tx_filt_pswords = params->tx_filt_pswords;
req.tx_atype = params->tx_atype;
req.tx_chan_type = params->tx_chan_type;
req.tx_supr_tdpkt = params->tx_supr_tdpkt;
req.tx_fetch_size = params->tx_fetch_size;
req.tx_credit_count = params->tx_credit_count;
req.txcq_qnum = params->txcq_qnum;
req.tx_priority = params->tx_priority;
req.tx_qos = params->tx_qos;
req.tx_orderid = params->tx_orderid;
req.fdepth = params->fdepth;
req.tx_sched_priority = params->tx_sched_priority;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send TX_CH_CFG fail %d\n", ret);
goto fail;
}
resp =
(struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;
fail:
dev_dbg(info->dev, "TX_CH_CFG: chn %u ret:%u\n", params->index, ret);
return ret;
}
static int ti_sci_cmd_rm_udmap_rx_ch_cfg(
const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params)
{
struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp *resp;
struct ti_sci_msg_rm_udmap_rx_ch_cfg_req req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_RM_UDMAP_RX_CH_CFG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message RX_CH_CFG alloc failed(%d)\n", ret);
return ret;
}
req.valid_params = params->valid_params;
req.nav_id = params->nav_id;
req.index = params->index;
req.rx_fetch_size = params->rx_fetch_size;
req.rxcq_qnum = params->rxcq_qnum;
req.rx_priority = params->rx_priority;
req.rx_qos = params->rx_qos;
req.rx_orderid = params->rx_orderid;
req.rx_sched_priority = params->rx_sched_priority;
req.flowid_start = params->flowid_start;
req.flowid_cnt = params->flowid_cnt;
req.rx_pause_on_err = params->rx_pause_on_err;
req.rx_atype = params->rx_atype;
req.rx_chan_type = params->rx_chan_type;
req.rx_ignore_short = params->rx_ignore_short;
req.rx_ignore_long = params->rx_ignore_long;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send RX_CH_CFG fail %d\n", ret);
goto fail;
}
resp =
(struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;
fail:
dev_dbg(info->dev, "RX_CH_CFG: chn %u ret:%d\n", params->index, ret);
return ret;
}
static int ti_sci_cmd_rm_udmap_rx_flow_cfg(
const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_flow_cfg *params)
{
struct ti_sci_msg_rm_udmap_flow_cfg_resp *resp;
struct ti_sci_msg_rm_udmap_flow_cfg_req req;
struct ti_sci_xfer *xfer;
struct ti_sci_info *info;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_RM_UDMAP_FLOW_CFG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(dev, "RX_FL_CFG: Message alloc failed(%d)\n", ret);
return ret;
}
req.valid_params = params->valid_params;
req.nav_id = params->nav_id;
req.flow_index = params->flow_index;
req.rx_einfo_present = params->rx_einfo_present;
req.rx_psinfo_present = params->rx_psinfo_present;
req.rx_error_handling = params->rx_error_handling;
req.rx_desc_type = params->rx_desc_type;
req.rx_sop_offset = params->rx_sop_offset;
req.rx_dest_qnum = params->rx_dest_qnum;
req.rx_src_tag_hi = params->rx_src_tag_hi;
req.rx_src_tag_lo = params->rx_src_tag_lo;
req.rx_dest_tag_hi = params->rx_dest_tag_hi;
req.rx_dest_tag_lo = params->rx_dest_tag_lo;
req.rx_src_tag_hi_sel = params->rx_src_tag_hi_sel;
req.rx_src_tag_lo_sel = params->rx_src_tag_lo_sel;
req.rx_dest_tag_hi_sel = params->rx_dest_tag_hi_sel;
req.rx_dest_tag_lo_sel = params->rx_dest_tag_lo_sel;
req.rx_fdq0_sz0_qnum = params->rx_fdq0_sz0_qnum;
req.rx_fdq1_qnum = params->rx_fdq1_qnum;
req.rx_fdq2_qnum = params->rx_fdq2_qnum;
req.rx_fdq3_qnum = params->rx_fdq3_qnum;
req.rx_ps_location = params->rx_ps_location;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(dev, "RX_FL_CFG: Mbox send fail %d\n", ret);
goto fail;
}
resp =
(struct ti_sci_msg_rm_udmap_flow_cfg_resp *)xfer->tx_message.buf;
ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;
fail:
dev_dbg(info->dev, "RX_FL_CFG: %u ret:%d\n", params->flow_index, ret);
return ret;
}
/*
* ti_sci_setup_ops() - Setup the operations structures
* @info: pointer to TISCI pointer
@ -1814,7 +2387,11 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
struct ti_sci_dev_ops *dops = &ops->dev_ops;
struct ti_sci_clk_ops *cops = &ops->clk_ops;
struct ti_sci_core_ops *core_ops = &ops->core_ops;
struct ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops;
struct ti_sci_proc_ops *pops = &ops->proc_ops;
struct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops;
struct ti_sci_rm_psil_ops *psilops = &ops->rm_psil_ops;
struct ti_sci_rm_udmap_ops *udmap_ops = &ops->rm_udmap_ops;
bops->board_config = ti_sci_cmd_set_board_config;
bops->board_config_rm = ti_sci_cmd_set_board_config_rm;
@ -1850,6 +2427,10 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
core_ops->reboot_device = ti_sci_cmd_core_reboot;
rm_core_ops->get_range = ti_sci_cmd_get_resource_range;
rm_core_ops->get_range_from_shost =
ti_sci_cmd_get_resource_range_from_shost;
pops->proc_request = ti_sci_cmd_proc_request;
pops->proc_release = ti_sci_cmd_proc_release;
pops->proc_handover = ti_sci_cmd_proc_handover;
@ -1857,6 +2438,16 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
rops->config = ti_sci_cmd_ring_config;
rops->get_config = ti_sci_cmd_ring_get_config;
psilops->pair = ti_sci_cmd_rm_psil_pair;
psilops->unpair = ti_sci_cmd_rm_psil_unpair;
udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;
udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;
udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;
}
/**
@ -1969,7 +2560,7 @@ static int ti_sci_of_to_info(struct udevice *dev, struct ti_sci_info *info)
}
info->host_id = dev_read_u32_default(dev, "ti,host-id",
info->desc->host_id);
info->desc->default_host_id);
info->is_secure = dev_read_bool(dev, "ti,secure-host");
@ -2009,17 +2600,164 @@ static int ti_sci_probe(struct udevice *dev)
return ret;
}
/*
* ti_sci_get_free_resource() - Get a free resource from TISCI resource.
* @res: Pointer to the TISCI resource
*
* Return: resource num if all went ok else TI_SCI_RESOURCE_NULL.
*/
u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
{
u16 set, free_bit;
for (set = 0; set < res->sets; set++) {
free_bit = find_first_zero_bit(res->desc[set].res_map,
res->desc[set].num);
if (free_bit != res->desc[set].num) {
set_bit(free_bit, res->desc[set].res_map);
return res->desc[set].start + free_bit;
}
}
return TI_SCI_RESOURCE_NULL;
}
/**
* ti_sci_release_resource() - Release a resource from TISCI resource.
* @res: Pointer to the TISCI resource
*/
void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
{
u16 set;
for (set = 0; set < res->sets; set++) {
if (res->desc[set].start <= id &&
(res->desc[set].num + res->desc[set].start) > id)
clear_bit(id - res->desc[set].start,
res->desc[set].res_map);
}
}
/**
* devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
* @handle: TISCI handle
* @dev: Device pointer to which the resource is assigned
* @of_prop: property name by which the resource are represented
*
* Note: This function expects of_prop to be in the form of tuples
* <type, subtype>. Allocates and initializes ti_sci_resource structure
* for each of_prop. Client driver can directly call
* ti_sci_(get_free, release)_resource apis for handling the resource.
*
* Return: Pointer to ti_sci_resource if all went well else appropriate
* error pointer.
*/
struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct udevice *dev, u32 dev_id, char *of_prop)
{
u32 resource_subtype;
u16 resource_type;
struct ti_sci_resource *res;
int sets, i, ret;
u32 *temp;
res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
if (!res)
return ERR_PTR(-ENOMEM);
sets = dev_read_size(dev, of_prop);
if (sets < 0) {
dev_err(dev, "%s resource type ids not available\n", of_prop);
return ERR_PTR(sets);
}
temp = malloc(sets);
sets /= sizeof(u32);
res->sets = sets;
res->desc = devm_kcalloc(dev, res->sets, sizeof(*res->desc),
GFP_KERNEL);
if (!res->desc)
return ERR_PTR(-ENOMEM);
ret = ti_sci_get_resource_type(handle_to_ti_sci_info(handle), dev_id,
&resource_type);
if (ret) {
dev_err(dev, "No valid resource type for %u\n", dev_id);
return ERR_PTR(-EINVAL);
}
ret = dev_read_u32_array(dev, of_prop, temp, res->sets);
if (ret)
return ERR_PTR(-EINVAL);
for (i = 0; i < res->sets; i++) {
resource_subtype = temp[i];
ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
resource_subtype,
&res->desc[i].start,
&res->desc[i].num);
if (ret) {
dev_err(dev, "type %d subtype %d not allocated for host %d\n",
resource_type, resource_subtype,
handle_to_ti_sci_info(handle)->host_id);
return ERR_PTR(ret);
}
dev_dbg(dev, "res type = %d, subtype = %d, start = %d, num = %d\n",
resource_type, resource_subtype, res->desc[i].start,
res->desc[i].num);
res->desc[i].res_map =
devm_kzalloc(dev, BITS_TO_LONGS(res->desc[i].num) *
sizeof(*res->desc[i].res_map), GFP_KERNEL);
if (!res->desc[i].res_map)
return ERR_PTR(-ENOMEM);
}
return res;
}
/* Description for K2G */
static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = {
.default_host_id = 2,
/* Conservative duration */
.max_rx_timeout_ms = 10000,
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
.max_msgs = 20,
.max_msg_size = 64,
.rm_type_map = NULL,
};
static struct ti_sci_rm_type_map ti_sci_am654_rm_type_map[] = {
{.dev_id = 56, .type = 0x00b}, /* GIC_IRQ */
{.dev_id = 179, .type = 0x000}, /* MAIN_NAV_UDMASS_IA0 */
{.dev_id = 187, .type = 0x009}, /* MAIN_NAV_RA */
{.dev_id = 188, .type = 0x006}, /* MAIN_NAV_UDMAP */
{.dev_id = 194, .type = 0x007}, /* MCU_NAV_UDMAP */
{.dev_id = 195, .type = 0x00a}, /* MCU_NAV_RA */
{.dev_id = 0, .type = 0x000}, /* end of table */
};
/* Description for AM654 */
static const struct ti_sci_desc ti_sci_sysfw_am654_desc = {
.host_id = 4,
.max_rx_timeout_us = 1000000,
static const struct ti_sci_desc ti_sci_pmmc_am654_desc = {
.default_host_id = 12,
/* Conservative duration */
.max_rx_timeout_ms = 10000,
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
.max_msgs = 20,
.max_msg_size = 60,
.rm_type_map = ti_sci_am654_rm_type_map,
};
static const struct udevice_id ti_sci_ids[] = {
{
.compatible = "ti,k2g-sci",
.data = (ulong)&ti_sci_sysfw_am654_desc
.data = (ulong)&ti_sci_pmmc_k2g_desc
},
{
.compatible = "ti,am654-sci",
.data = (ulong)&ti_sci_pmmc_am654_desc
},
{ /* Sentinel */ },
};

642
drivers/firmware/ti_sci.h
View File

@ -50,6 +50,34 @@
#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
/* Resource Management Requests */
#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
/* NAVSS resource management */
/* Ringacc requests */
#define TI_SCI_MSG_RM_RING_CFG 0x1110
#define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
/* PSI-L requests */
#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
/**
* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
* @type: Type of messages: One of TI_SCI_MSG* values
@ -505,6 +533,45 @@ struct ti_sci_msg_resp_get_clock_freq {
u64 freq_hz;
} __packed;
#define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
/**
* struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
* range of resources.
* @hdr: Generic Header
* @type: Unique resource assignment type
* @subtype: Resource assignment subtype within the resource type.
* @secondary_host: Host processing entity to which the resources are
* allocated. This is required only when the destination
* host id id different from ti sci interface host id,
* else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
*
* Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
* resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
*/
struct ti_sci_msg_req_get_resource_range {
struct ti_sci_msg_hdr hdr;
#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
u16 type;
u8 subtype;
u8 secondary_host;
} __packed;
/**
* struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
* @hdr: Generic Header
* @range_start: Start index of the resource range.
* @range_num: Number of resources in the range.
*
* Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
*/
struct ti_sci_msg_resp_get_resource_range {
struct ti_sci_msg_hdr hdr;
u16 range_start;
u16 range_num;
} __packed;
#define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
#define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
#define TISCI_ADDR_HIGH_SHIFT 32
@ -677,4 +744,579 @@ struct ti_sci_msg_resp_get_proc_boot_status {
u32 status_flags;
} __packed;
/**
* struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
*
* Configures the non-real-time registers of a Navigator Subsystem ring.
* @hdr: Generic Header
* @valid_params: Bitfield defining validity of ring configuration parameters.
* The ring configuration fields are not valid, and will not be used for
* ring configuration, if their corresponding valid bit is zero.
* Valid bit usage:
* 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
* 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
* 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
* 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
* 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
* 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
* @index: ring index to be configured.
* @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
* RING_BA_LO register
* @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
* RING_BA_HI register.
* @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
* modes.
* @mode: Specifies the mode the ring is to be configured.
* @size: Specifies encoded ring element size. To calculate the encoded size use
* the formula (log2(size_bytes) - 2), where size_bytes cannot be
* greater than 256.
* @order_id: Specifies the ring's bus order ID.
*/
struct ti_sci_msg_rm_ring_cfg_req {
struct ti_sci_msg_hdr hdr;
u32 valid_params;
u16 nav_id;
u16 index;
u32 addr_lo;
u32 addr_hi;
u32 count;
u8 mode;
u8 size;
u8 order_id;
} __packed;
/**
* struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
*
* @hdr: Generic Header
*/
struct ti_sci_msg_rm_ring_cfg_resp {
struct ti_sci_msg_hdr hdr;
} __packed;
/**
* struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
*
* Gets the configuration of the non-real-time register fields of a ring. The
* host, or a supervisor of the host, who owns the ring must be the requesting
* host. The values of the non-real-time registers are returned in
* @ti_sci_msg_rm_ring_get_cfg_resp.
*
* @hdr: Generic Header
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
* @index: ring index.
*/
struct ti_sci_msg_rm_ring_get_cfg_req {
struct ti_sci_msg_hdr hdr;
u16 nav_id;
u16 index;
} __packed;
/**
* struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
*
* Response received by host processor after RM has handled
* @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
* non-real-time register values.
*
* @hdr: Generic Header
* @addr_lo: Ring 32 LSBs of base address
* @addr_hi: Ring 16 MSBs of base address.
* @count: Ring number of elements.
* @mode: Ring mode.
* @size: encoded Ring element size
* @order_id: ing order ID.
*/
struct ti_sci_msg_rm_ring_get_cfg_resp {
struct ti_sci_msg_hdr hdr;
u32 addr_lo;
u32 addr_hi;
u32 count;
u8 mode;
u8 size;
u8 order_id;
} __packed;
/**
* struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
* thread
* @hdr: Generic Header
* @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
* used to pair the source and destination threads.
* @src_thread: PSI-L source thread ID within the PSI-L System thread map.
*
* UDMAP transmit channels mapped to source threads will have their
* TCHAN_THRD_ID register programmed with the destination thread if the pairing
* is successful.
* @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
* PSI-L destination threads start at index 0x8000. The request is NACK'd if
* the destination thread is not greater than or equal to 0x8000.
*
* UDMAP receive channels mapped to destination threads will have their
* RCHAN_THRD_ID register programmed with the source thread if the pairing
* is successful.
*
* Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
* message.
*/
struct ti_sci_msg_psil_pair {
struct ti_sci_msg_hdr hdr;
u32 nav_id;
u32 src_thread;
u32 dst_thread;
} __packed;
/**
* struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
* destination thread
* @hdr: Generic Header
* @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
* used to unpair the source and destination threads.
* @src_thread: PSI-L source thread ID within the PSI-L System thread map.
*
* UDMAP transmit channels mapped to source threads will have their
* TCHAN_THRD_ID register cleared if the unpairing is successful.
*
* @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
* PSI-L destination threads start at index 0x8000. The request is NACK'd if
* the destination thread is not greater than or equal to 0x8000.
*
* UDMAP receive channels mapped to destination threads will have their
* RCHAN_THRD_ID register cleared if the unpairing is successful.
*
* Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
* message.
*/
struct ti_sci_msg_psil_unpair {
struct ti_sci_msg_hdr hdr;
u32 nav_id;
u32 src_thread;
u32 dst_thread;
} __packed;
/**
* Configures a Navigator Subsystem UDMAP transmit channel
*
* Configures the non-real-time registers of a Navigator Subsystem UDMAP
* transmit channel. The channel index must be assigned to the host defined
* in the TISCI header via the RM board configuration resource assignment
* range list.
*
* @hdr: Generic Header
*
* @valid_params: Bitfield defining validity of tx channel configuration
* parameters. The tx channel configuration fields are not valid, and will not
* be used for ch configuration, if their corresponding valid bit is zero.
* Valid bit usage:
* 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
* 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
* 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
* 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
* 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
* 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
* 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
* 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
* 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
* 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
* 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
*
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
*
* @index: UDMAP transmit channel index.
*
* @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
* be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
* register.
*
* @tx_filt_einfo: UDMAP transmit channel extended packet information passing
* configuration to be programmed into the tx_filt_einfo field of the
* channel's TCHAN_TCFG register.
*
* @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
* configuration to be programmed into the tx_filt_pswords field of the
* channel's TCHAN_TCFG register.
*
* @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
* interpretation configuration to be programmed into the tx_atype field of
* the channel's TCHAN_TCFG register.
*
* @tx_chan_type: UDMAP transmit channel functional channel type and work
* passing mechanism configuration to be programmed into the tx_chan_type
* field of the channel's TCHAN_TCFG register.
*
* @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
* configuration to be programmed into the tx_supr_tdpkt field of the channel's
* TCHAN_TCFG register.
*
* @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
* fetch configuration to be programmed into the tx_fetch_size field of the
* channel's TCHAN_TCFG register. The user must make sure to set the maximum
* word count that can pass through the channel for any allowed descriptor type.
*
* @tx_credit_count: UDMAP transmit channel transfer request credit count
* configuration to be programmed into the count field of the TCHAN_TCREDIT
* register. Specifies how many credits for complete TRs are available.
*
* @txcq_qnum: UDMAP transmit channel completion queue configuration to be
* programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
* completion queue must be assigned to the host, or a subordinate of the host,
* requesting configuration of the transmit channel.
*
* @tx_priority: UDMAP transmit channel transmit priority value to be programmed
* into the priority field of the channel's TCHAN_TPRI_CTRL register.
*
* @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
* qos field of the channel's TCHAN_TPRI_CTRL register.
*
* @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
* the orderid field of the channel's TCHAN_TPRI_CTRL register.
*
* @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
* into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
* Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
* section of the TRM for restrictions regarding this parameter.
*
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
* configuration to be programmed into the priority field of the channel's
* TCHAN_TST_SCHED register.
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
u32 valid_params;
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
u8 tx_filt_einfo;
u8 tx_filt_pswords;
u8 tx_atype;
u8 tx_chan_type;
u8 tx_supr_tdpkt;
u16 tx_fetch_size;
u8 tx_credit_count;
u16 txcq_qnum;
u8 tx_priority;
u8 tx_qos;
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
} __packed;
/**
* Response to configuring a UDMAP transmit channel.
*
* @hdr: Standard TISCI header
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
struct ti_sci_msg_hdr hdr;
} __packed;
/**
* Configures a Navigator Subsystem UDMAP receive channel
*
* Configures the non-real-time registers of a Navigator Subsystem UDMAP
* receive channel. The channel index must be assigned to the host defined
* in the TISCI header via the RM board configuration resource assignment
* range list.
*
* @hdr: Generic Header
*
* @valid_params: Bitfield defining validity of rx channel configuration
* parameters.
* The rx channel configuration fields are not valid, and will not be used for
* ch configuration, if their corresponding valid bit is zero.
* Valid bit usage:
* 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
* 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
* 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
* 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
* 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
* 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
* 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
* 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
* 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
* 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
* 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
* 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
* 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
*
* @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
*
* @index: UDMAP receive channel index.
*
* @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
* fetch configuration to be programmed into the rx_fetch_size field of the
* channel's RCHAN_RCFG register.
*
* @rxcq_qnum: UDMAP receive channel completion queue configuration to be
* programmed into the rxcq_qnum field of the RCHAN_RCQ register.
* The specified completion queue must be assigned to the host, or a subordinate
* of the host, requesting configuration of the receive channel.
*
* @rx_priority: UDMAP receive channel receive priority value to be programmed
* into the priority field of the channel's RCHAN_RPRI_CTRL register.
*
* @rx_qos: UDMAP receive channel receive qos value to be programmed into the
* qos field of the channel's RCHAN_RPRI_CTRL register.
*
* @rx_orderid: UDMAP receive channel bus order id value to be programmed into
* the orderid field of the channel's RCHAN_RPRI_CTRL register.
*
* @rx_sched_priority: UDMAP receive channel rx scheduling priority
* configuration to be programmed into the priority field of the channel's
* RCHAN_RST_SCHED register.
*
* @flowid_start: UDMAP receive channel additional flows starting index
* configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
* register. Specifies the starting index for flow IDs the receive channel is to
* make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
* set as valid and configured together. The starting flow ID set by
* @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
* of flows beyond the default flows statically mapped to receive channels.
* The additional flows must be assigned to the host, or a subordinate of the
* host, requesting configuration of the receive channel.
*
* @flowid_cnt: UDMAP receive channel additional flows count configuration to
* program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
* This field specifies how many flow IDs are in the additional contiguous range
* of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
* set as valid and configured together. Disabling the valid_params field bit
* for flowid_cnt indicates no flow IDs other than the default are to be
* allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
* cannot be greater than the number of receive flows in the receive channel's
* Navigator Subsystem. The additional flows must be assigned to the host, or a
* subordinate of the host, requesting configuration of the receive channel.
*
* @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
* programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
* register.
*
* @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
* interpretation configuration to be programmed into the rx_atype field of the
* channel's RCHAN_RCFG register.
*
* @rx_chan_type: UDMAP receive channel functional channel type and work passing
* mechanism configuration to be programmed into the rx_chan_type field of the
* channel's RCHAN_RCFG register.
*
* @rx_ignore_short: UDMAP receive channel short packet treatment configuration
* to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
*
* @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
* be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
*/
struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
u32 valid_params;
u16 nav_id;
u16 index;
u16 rx_fetch_size;
u16 rxcq_qnum;
u8 rx_priority;
u8 rx_qos;
u8 rx_orderid;
u8 rx_sched_priority;
u16 flowid_start;
u16 flowid_cnt;
u8 rx_pause_on_err;
u8 rx_atype;
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
} __packed;
/**
* Response to configuring a UDMAP receive channel.
*
* @hdr: Standard TISCI header
*/
struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
struct ti_sci_msg_hdr hdr;
} __packed;
/**
* Configures a Navigator Subsystem UDMAP receive flow
*
* Configures a Navigator Subsystem UDMAP receive flow's registers.
* Configuration does not include the flow registers which handle size-based
* free descriptor queue routing.
*
* The flow index must be assigned to the host defined in the TISCI header via
* the RM board configuration resource assignment range list.
*
* @hdr: Standard TISCI header
*
* @valid_params
* Bitfield defining validity of rx flow configuration parameters. The
* rx flow configuration fields are not valid, and will not be used for flow
* configuration, if their corresponding valid bit is zero. Valid bit usage:
* 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
* 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
* 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
* 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
* 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
* 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
* 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
* 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
* 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
* 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
* 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
* 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
* 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
* 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
* 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
* 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
* 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
* 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
* 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
*
* @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
* allocated
*
* @flow_index: UDMAP receive flow index for non-optional configuration.
*
* @rx_einfo_present:
* UDMAP receive flow extended packet info present configuration to be
* programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
*
* @rx_psinfo_present:
* UDMAP receive flow PS words present configuration to be programmed into the
* rx_psinfo_present field of the flow's RFLOW_RFA register.
*
* @rx_error_handling:
* UDMAP receive flow error handling configuration to be programmed into the
* rx_error_handling field of the flow's RFLOW_RFA register.
*
* @rx_desc_type:
* UDMAP receive flow descriptor type configuration to be programmed into the
* rx_desc_type field field of the flow's RFLOW_RFA register.
*
* @rx_sop_offset:
* UDMAP receive flow start of packet offset configuration to be programmed
* into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
* section of the TRM for more information on this setting. Valid values for
* this field are 0-255 bytes.
*
* @rx_dest_qnum:
* UDMAP receive flow destination queue configuration to be programmed into the
* rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
* destination queue must be valid within the Navigator Subsystem and must be
* owned by the host, or a subordinate of the host, requesting allocation and
* configuration of the receive flow.
*
* @rx_src_tag_hi:
* UDMAP receive flow source tag high byte constant configuration to be
* programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
* See the UDMAP section of the TRM for more information on this setting.
*
* @rx_src_tag_lo:
* UDMAP receive flow source tag low byte constant configuration to be
* programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
* See the UDMAP section of the TRM for more information on this setting.
*
* @rx_dest_tag_hi:
* UDMAP receive flow destination tag high byte constant configuration to be
* programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
* See the UDMAP section of the TRM for more information on this setting.
*
* @rx_dest_tag_lo:
* UDMAP receive flow destination tag low byte constant configuration to be
* programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
* See the UDMAP section of the TRM for more information on this setting.
*
* @rx_src_tag_hi_sel:
* UDMAP receive flow source tag high byte selector configuration to be
* programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
* the UDMAP section of the TRM for more information on this setting.
*
* @rx_src_tag_lo_sel:
* UDMAP receive flow source tag low byte selector configuration to be
* programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
* the UDMAP section of the TRM for more information on this setting.
*
* @rx_dest_tag_hi_sel:
* UDMAP receive flow destination tag high byte selector configuration to be
* programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
* the UDMAP section of the TRM for more information on this setting.
*
* @rx_dest_tag_lo_sel:
* UDMAP receive flow destination tag low byte selector configuration to be
* programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
* the UDMAP section of the TRM for more information on this setting.
*
* @rx_fdq0_sz0_qnum:
* UDMAP receive flow free descriptor queue 0 configuration to be programmed
* into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
* UDMAP section of the TRM for more information on this setting. The specified
* free queue must be valid within the Navigator Subsystem and must be owned
* by the host, or a subordinate of the host, requesting allocation and
* configuration of the receive flow.
*
* @rx_fdq1_qnum:
* UDMAP receive flow free descriptor queue 1 configuration to be programmed
* into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
* UDMAP section of the TRM for more information on this setting. The specified
* free queue must be valid within the Navigator Subsystem and must be owned
* by the host, or a subordinate of the host, requesting allocation and
* configuration of the receive flow.
*
* @rx_fdq2_qnum:
* UDMAP receive flow free descriptor queue 2 configuration to be programmed
* into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
* UDMAP section of the TRM for more information on this setting. The specified
* free queue must be valid within the Navigator Subsystem and must be owned
* by the host, or a subordinate of the host, requesting allocation and
* configuration of the receive flow.
*
* @rx_fdq3_qnum:
* UDMAP receive flow free descriptor queue 3 configuration to be programmed
* into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
* UDMAP section of the TRM for more information on this setting. The specified
* free queue must be valid within the Navigator Subsystem and must be owned
* by the host, or a subordinate of the host, requesting allocation and
* configuration of the receive flow.
*
* @rx_ps_location:
* UDMAP receive flow PS words location configuration to be programmed into the
* rx_ps_location field of the flow's RFLOW_RFA register.
*/
struct ti_sci_msg_rm_udmap_flow_cfg_req {
struct ti_sci_msg_hdr hdr;
u32 valid_params;
u16 nav_id;
u16 flow_index;
u8 rx_einfo_present;
u8 rx_psinfo_present;
u8 rx_error_handling;
u8 rx_desc_type;
u16 rx_sop_offset;
u16 rx_dest_qnum;
u8 rx_src_tag_hi;
u8 rx_src_tag_lo;
u8 rx_dest_tag_hi;
u8 rx_dest_tag_lo;
u8 rx_src_tag_hi_sel;
u8 rx_src_tag_lo_sel;
u8 rx_dest_tag_hi_sel;
u8 rx_dest_tag_lo_sel;
u16 rx_fdq0_sz0_qnum;
u16 rx_fdq1_qnum;
u16 rx_fdq2_qnum;
u16 rx_fdq3_qnum;
u8 rx_ps_location;
} __packed;
/**
* Response to configuring a Navigator Subsystem UDMAP receive flow
*
* @hdr: Standard TISCI header
*/
struct ti_sci_msg_rm_udmap_flow_cfg_resp {
struct ti_sci_msg_hdr hdr;
} __packed;
#endif /* __TI_SCI_H */

300
include/linux/soc/ti/ti_sci_protocol.h
View File

@ -212,6 +212,31 @@ struct ti_sci_clk_ops {
u64 *current_freq);
};
/**
* struct ti_sci_rm_core_ops - Resource management core operations
* @get_range: Get a range of resources belonging to ti sci host.
* @get_rage_from_shost: Get a range of resources belonging to
* specified host id.
* - s_host: Host processing entity to which the
* resources are allocated
*
* NOTE: for these functions, all the parameters are consolidated and defined
* as below:
* - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* - dev_id: TISCI device ID.
* - subtype: Resource assignment subtype that is being requested
* from the given device.
* - range_start: Start index of the resource range
* - range_end: Number of resources in the range
*/
struct ti_sci_rm_core_ops {
int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
u8 subtype, u16 *range_start, u16 *range_num);
int (*get_range_from_shost)(const struct ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
u16 *range_start, u16 *range_num);
};
/**
* struct ti_sci_core_ops - SoC Core Operations
* @reboot_device: Reboot the SoC
@ -257,6 +282,230 @@ struct ti_sci_proc_ops {
u32 *sts_flags);
};
#define TI_SCI_RING_MODE_RING (0)
#define TI_SCI_RING_MODE_MESSAGE (1)
#define TI_SCI_RING_MODE_CREDENTIALS (2)
#define TI_SCI_RING_MODE_QM (3)
#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
/* RA config.count parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
/* RA config.size parameter is valid for RM ring configure TI_SCI message */
#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
/* RA config.order_id parameter is valid for RM ring configure TISCI message */
#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
/**
* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
* @config: configure the SoC Navigator Subsystem Ring Accelerator ring
* @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
* configuration
*/
struct ti_sci_rm_ringacc_ops {
int (*config)(const struct ti_sci_handle *handle,
u32 valid_params, u16 nav_id, u16 index,
u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
u8 size, u8 order_id
);
int (*get_config)(const struct ti_sci_handle *handle,
u32 nav_id, u32 index, u8 *mode,
u32 *addr_lo, u32 *addr_hi, u32 *count,
u8 *size, u8 *order_id);
};
/**
* struct ti_sci_rm_psil_ops - PSI-L thread operations
* @pair: pair PSI-L source thread to a destination thread.
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
* TCHAN_THRD_ID register is updated.
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
* RCHAN_THRD_ID register is updated.
* @unpair: unpair PSI-L source thread from a destination thread.
* If the src_thread is mapped to UDMA tchan, the corresponding channel's
* TCHAN_THRD_ID register is cleared.
* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
* RCHAN_THRD_ID register is cleared.
*/
struct ti_sci_rm_psil_ops {
int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
u32 src_thread, u32 dst_thread);
int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
u32 src_thread, u32 dst_thread);
};
/* UDMAP channel types */
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
/* UDMAP channel atypes */
#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0
#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1
#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2
/* UDMAP channel scheduling priorities */
#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0
#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1
#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2
#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
/* UDMAP TX/RX channel valid_params common declarations */
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
/**
* Configures a Navigator Subsystem UDMAP transmit channel
*
* Configures a Navigator Subsystem UDMAP transmit channel registers.
* See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
u8 tx_filt_einfo;
u8 tx_filt_pswords;
u8 tx_atype;
u8 tx_chan_type;
u8 tx_supr_tdpkt;
u16 tx_fetch_size;
u8 tx_credit_count;
u16 txcq_qnum;
u8 tx_priority;
u8 tx_qos;
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
};
/**
* Configures a Navigator Subsystem UDMAP receive channel
*
* Configures a Navigator Subsystem UDMAP receive channel registers.
* See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
*/
struct ti_sci_msg_rm_udmap_rx_ch_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
u16 nav_id;
u16 index;
u16 rx_fetch_size;
u16 rxcq_qnum;
u8 rx_priority;
u8 rx_qos;
u8 rx_orderid;
u8 rx_sched_priority;
u16 flowid_start;
u16 flowid_cnt;
u8 rx_pause_on_err;
u8 rx_atype;
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
};
/**
* Configures a Navigator Subsystem UDMAP receive flow
*
* Configures a Navigator Subsystem UDMAP receive flow's registers.
* See @tis_ci_msg_rm_udmap_flow_cfg_req
*/
struct ti_sci_msg_rm_udmap_flow_cfg {
u32 valid_params;
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
u16 nav_id;
u16 flow_index;
u8 rx_einfo_present;
u8 rx_psinfo_present;
u8 rx_error_handling;
u8 rx_desc_type;
u16 rx_sop_offset;
u16 rx_dest_qnum;
u8 rx_src_tag_hi;
u8 rx_src_tag_lo;
u8 rx_dest_tag_hi;
u8 rx_dest_tag_lo;
u8 rx_src_tag_hi_sel;
u8 rx_src_tag_lo_sel;
u8 rx_dest_tag_hi_sel;
u8 rx_dest_tag_lo_sel;
u16 rx_fdq0_sz0_qnum;
u16 rx_fdq1_qnum;
u16 rx_fdq2_qnum;
u16 rx_fdq3_qnum;
u8 rx_ps_location;
};
/**
* struct ti_sci_rm_udmap_ops - UDMA Management operations
* @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
* @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
* @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow.
*/
struct ti_sci_rm_udmap_ops {
int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
int (*rx_flow_cfg)(
const struct ti_sci_handle *handle,
const struct ti_sci_msg_rm_udmap_flow_cfg *params);
};
/**
* struct ti_sci_ops - Function support for TI SCI
* @board_ops: Miscellaneous operations
@ -264,6 +513,7 @@ struct ti_sci_proc_ops {
* @clk_ops: Clock specific operations
* @core_ops: Core specific operations
* @proc_ops: Processor specific operations
* @ring_ops: Ring Accelerator Management operations
*/
struct ti_sci_ops {
struct ti_sci_board_ops board_ops;
@ -271,6 +521,10 @@ struct ti_sci_ops {
struct ti_sci_clk_ops clk_ops;
struct ti_sci_core_ops core_ops;
struct ti_sci_proc_ops proc_ops;
struct ti_sci_rm_core_ops rm_core_ops;
struct ti_sci_rm_ringacc_ops rm_ring_ops;
struct ti_sci_rm_psil_ops rm_psil_ops;
struct ti_sci_rm_udmap_ops rm_udmap_ops;
};
/**
@ -283,12 +537,42 @@ struct ti_sci_handle {
struct ti_sci_version_info version;
};
#define TI_SCI_RESOURCE_NULL 0xffff
/**
* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
* @start: Start index of the resource.
* @num: Number of resources.
* @res_map: Bitmap to manage the allocation of these resources.
*/
struct ti_sci_resource_desc {
u16 start;
u16 num;
unsigned long *res_map;
};
/**
* struct ti_sci_resource - Structure representing a resource assigned
* to a device.
* @sets: Number of sets available from this resource type
* @desc: Array of resource descriptors.
*/
struct ti_sci_resource {
u16 sets;
struct ti_sci_resource_desc *desc;
};
#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
const char *property);
u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct udevice *dev, u32 dev_id, char *of_prop);
#else /* CONFIG_TI_SCI_PROTOCOL */
@ -309,6 +593,22 @@ const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
{
return ERR_PTR(-EINVAL);
}
static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
{
return TI_SCI_RESOURCE_NULL;
}
static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
{
}
static inline struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct udevice *dev, u32 dev_id, char *of_prop)
{
return ERR_PTR(-EINVAL);
}
#endif /* CONFIG_TI_SCI_PROTOCOL */
#endif /* __TISCI_PROTOCOL_H */