Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
Since commit ddaf5c8f30
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of "Invalid MAINTAINERS address: '-'"
error messages for patches with global changes.
It takes too long for Patman to process them.
Anyway, "M: -" does not carry any important information.
Rather, it is just like a place holder in case of assigning
a new board maintainer. Let's comment out.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The "S: Orphan" in MAINTAINERS means that the maintainer in the
"M:" field is unreachable (i.e. the email address is not working).
(Refer to the definition of "Orphan" adopted in U-Boot
in the log of commit 31f1b654b2,
"boards.cfg: move boards with invalid emails to Orphan")
For patch files adding global changes, scripts/get_maintainer.pl
adds bunch of such invalid email addresses, which results in
tons of annoying bounce emails.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '
/^M:[[:blank:]]/ {
N
/S:[[:blank:]]Orphan/s/^/#/
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.
Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.
I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5
Add support of above sgmii interfaces
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.
This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versa
This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.
So, update gd->env_addr to reflect correct address.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
- Use _defconfig instead of _config, but still _config is working.
- Corrected README.sandbox path in ./README
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add NOR flash hardware init function, including SMC and PIO
configuration.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Cc: David Feng <fenghua@phytium.com.cn>
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
if (gpio_cfg[board].leds[i])
^
board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
for (i = 0; i < 4; i++) {
^
Fix this by making the upper bound of the loop match the array size.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support for SATA.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add ethernet support for Compulab CM-FX6 CoM
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.
This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
