board/t1040qds: Add sgmii ports support in 0xA7 protocol

T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5

Add support of above sgmii interfaces

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
This commit is contained in:
Priyanka Jain 2014-09-08 13:20:52 +05:30 committed by York Sun
parent 92f7fed4f7
commit 5273aa3834
2 changed files with 4 additions and 2 deletions

View File

@ -241,6 +241,8 @@ static void initialize_lane_to_slot(void)
break;
case 0xA7:
lane_to_slot[1] = 7;
lane_to_slot[2] = 6;
lane_to_slot[3] = 5;
lane_to_slot[7] = 7;
break;
case 0xAA:
@ -410,6 +412,8 @@ void t1040_handle_phy_interface_sgmii(int i)
fm_info_set_phy_address(i, riser_phy_addr[1]);
if (FM1_DTSEC3 == i)
fm_info_set_phy_address(i, riser_phy_addr[2]);
if (FM1_DTSEC5 == i)
fm_info_set_phy_address(i, riser_phy_addr[3]);
mdio_mux[i] = EMI1_SLOT7;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));

View File

@ -49,8 +49,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
switch (port) {